Multi-layer electrode to improve performance of ferroelectric memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
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Abstract
Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.
Claims20
A memory device, comprising:
- a first bottom electrode layer overlying a substrate, wherein the first bottom electrode layer comprises a first non-oxide conductive material;
- a ferroelectric switching layer disposed over the first bottom electrode layer;
- a first top electrode layer disposed over the ferroelectric switching layer;
- and
- a second bottom electrode layer disposed between the first bottom electrode layer and the ferroelectric switching layer, wherein the second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer, wherein the second bottom electrode layer contacts a bottom surface of the ferroelectric switching layer and comprises a second non-oxide conductive material different from the first non-oxide conductive material.
An integrated chip, comprising:
- a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate;
- a memory cell disposed over the lower interconnect, wherein the memory cell comprises a ferroelectric switching layer disposed between a multi-layer bottom electrode and a multi-layer top electrode;
- and
- wherein the multi-layer bottom electrode comprises a first bottom electrode layer and a second bottom electrode layer disposed between the first bottom electrode layer and the ferroelectric switching layer, wherein the multi-layer top electrode comprises a first top electrode layer and a second top electrode layer disposed between the first top electrode layer and the ferroelectric switching layer, wherein the first bottom electrode layer and the first top electrode layer comprise a first material and the second bottom electrode layer and the second top electrode layer comprise a second material different than the first material, wherein the second bottom electrode layer and the second top electrode layer are respectively configured to prevent oxidation of the first bottom electrode layer and the first top electrode layer.
An integrated chip, comprising:
- a lower interconnect over a substrate;
- a lower insulating structure over the lower interconnect;
- a multi-layer bottom electrode over the lower interconnect and comprising a first bottom electrode layer stacked with a second bottom electrode layer, wherein the multi-layer bottom electrode comprises a central region extending through the lower insulating structure to contact the lower interconnect and an outer region disposed on a top surface of the lower insulating structure;
- a ferroelectric layer on the multi-layer bottom electrode;
- and
- a multi-layer top electrode on the ferroelectric layer, wherein a bottom surface of the multi-layer top electrode is below the top surface of the lower insulating structure, wherein the multi-layer top electrode comprises a first top electrode layer stacked with a second top electrode layer, wherein a first Gibbs free energy of the first top and bottom electrode layers is less than a second Gibbs free energy of the second top and bottom electrode layers.
Dependencies are inferred from the claim text.