Method of forming multiple-Vt FETS for CMOS circuit applications
AssigneeSamsung Electronics Co., Ltd.
InventorsWei-E Wang, Mark S. Rodder
Life of this patent
Estimating the term…
Abstract
A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.
Claims19
A field-effect transistor (FET) device having a modulated Vt, the FET device comprising:
- a source electrode;
- a drain electrode;
- a channel region between the source electrode and the drain electrode;
- and
- a gate stack on the channel region, the gate stack comprising:
- a layer combination to shift the modulated Vt in a first direction and by a first magnitude, the layer combination comprising:
- an ultrathin dielectric dipole layer;
- and
- a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, wherein the ultrathin dielectric dipole layer contacts the channel region, and
- a gate metal layer on the layer combination and to shift the modulated Vt in a second direction opposite the first direction and by a second magnitude, a value of the second magnitude being smaller than a value of the first magnitude,
- wherein the gate metal layer is configured to shift the modulated Vt in the second direction simultaneously with the shift of the modulated Vt in the first direction to provide a predetermined modulated Vt value, and
- wherein the gate metal layer and the layer combination are configured to shift the modulated Vt independently from each other.
A method of manufacturing a field-effect transistor (FET) device having a modulated Vt, the method comprising:
- providing a channel region between a source electrode and a drain electrode,
- forming a layer combination on the channel region, the layer combination to shift the modulated Vt in a first direction by a first magnitude, by:
- depositing an ultrathin dielectric dipole layer such that the ultrathin dielectric dipole layer contacts the channel region;
- and
- depositing a first high-k (HK) insulating layer on the ultrathin dielectric dipole layer;
- and
- depositing a gate metal layer on the HK insulating layer to shift the modulated Vt in a second direction opposite the first direction and by a second magnitude, a value of the second magnitude being smaller than a value of the first magnitude,
- wherein the FET device is not annealed at a temperature above 500° C.,
- wherein the gate metal layer is configured to shift the modulated Vt in the second direction simultaneously with the shift of the modulated Vt in the first direction to provide a predetermined modulated Vt value, and
- wherein the gate metal layer and the layer combination are configured to shift the modulated Vt independently from each other.
Dependencies are inferred from the claim text.