Semiconductor devices including separation structure

A semiconductor device, comprising:

• a plurality of active regions on a substrate;
• a gate electrode intersecting the plurality of active regions;
• a plurality of source/drain regions on the plurality of active regions, such that the plurality of source/drain regions are adjacent to opposite sides of the gate electrode and the gate electrode is between the plurality of source/drain regions;
• and
• a plurality of separation structures, each separate separation structure of the plurality of separation structures between proximate source/drain regions of the plurality of source/drain regions,
• wherein each separation structure of the plurality of separation structures includes
• an insulating pattern that includes a first side surface and a second side surface that are opposite side surfaces of the insulating pattern and are adjacent to separate, respective source/drain regions of the proximate source/drain regions, and
• a spacer layer on the first side surface and the second side surface, and the spacer layer at least partially between the insulating pattern and the separate, respective source/drain regions,
• wherein an uppermost end of the insulating pattern is farther from a lower surface of the substrate than a first upper surface of the spacer layer that is proximate to the first side surface and the second side surface,
• wherein the first side surface and the second side surface of the insulating pattern each include
• a lower portion contacting the spacer layer,
• a middle portion contacting the respective source/drain regions of the proximate source/drain regions, and
• an upper portion spaced apart from the respective source/drain regions of the proximate source/drain regions,
• wherein a lower surface of the spacer layer is further from the lower surface of the substrate than a central portion of a lower surface of the respective source/drain regions of the proximate source/drain regions,
• wherein the spacer layer includes
• a first spacer layer, and
• a second spacer layer between the first spacer layer and the insulating pattern,
• wherein each of an upper surface of the first spacer layer and an upper surface of the second spacer layer that is proximate to the first side surface of the insulating pattern and the second side surface of the insulating pattern vertically overlaps and entirely contacts an outer portion of the respective source/drain regions of the proximate source/drain regions, and
• wherein the upper surface of the second spacer layer is closer to the lower surface of the substrate than the upper surface of the first spacer layer.