Semiconductor structure with enhanced placeholder position margin

A semiconductor structure comprising:

• a nanosheet transistor comprising a plurality of spaced apart and vertically stacked semiconductor channel material nanosheets, a gate structure wrapped around each semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets and a pair of source/drain regions;
• upper inner spacers located between each vertically stacked pair of semiconductor channel material nanosheets of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets and beneath a bottommost semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets;
• lower inner spacers located beneath bottommost upper inner spacers, wherein each of the lower inner spacers is vertically separated from the bottommost upper inner spacers by a semiconductor pedestal;
• and
• a backside source/drain contact structure contacting a first source/drain region of the pair of source/drain regions, wherein the backside source/drain contact structure has a first portion and a second portion, wherein the second portion of the backside source/drain contact structure is confined by the bottommost upper inner spacers, the lower inner spacers and the semiconductor pedestal.