Sacrificial gate capping layer for gate protection during source/drain contact opening
AssigneeTokyo Electron Limited
InventorsYun Han, Eric Chih-Fang Liu, Kai-Hung Yu, Shihsheng Chang, Alok Ranjan
Life of this patent
Estimating the term…
Loading patent…
AssigneeTokyo Electron Limited
InventorsYun Han, Eric Chih-Fang Liu, Kai-Hung Yu, Shihsheng Chang, Alok Ranjan
Estimating the term…
A method including providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate, each of the source/drain contact regions being recessed within a respective opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the opening and adjacent metal gate stacks provide sidewalls, and a dielectric covering the substrate such that the dielectric fills each opening. The substrate is exposed to an initial plasma etch process to remove a first portion of the dielectric from each opening down to a first depth, and a sacrificial gate capping layer is formed on the substrate while leaving each of the openings uncovered. The substrate is exposed to another plasma etch process to remove the sacrificial gate capping layer while removing a second portion of the dielectric from each opening down to a second depth.
A method comprising:
A method comprising:
Dependencies are inferred from the claim text.