Stacked transistor isolation features and methods of forming the same

A method comprising:

• patterning an upper semiconductor nanostructure, a lower semiconductor nanostructure, and a dummy nanostructure, the dummy nanostructure being disposed between the upper semiconductor nanostructure and the lower semiconductor nanostructure, the upper semiconductor nanostructure having a first thickness, the lower semiconductor nanostructure having a second thickness, the dummy nanostructure having a third thickness, the third thickness being larger than the first thickness and the second thickness, the dummy nanostructure comprising a superlattice structure of alternating layers of a first material and a second material, the first material being different from the second material;
• etching the dummy nanostructure to form an opening;
• and
• forming an isolation structure in the opening.

A method comprising:

• patterning a semiconductor nanostructure, first dummy nanostructure, and a second dummy nanostructure, the semiconductor nanostructure being disposed between the first dummy nanostructure and the second dummy nanostructure, the semiconductor nanostructure comprising a first material with a first lattice constant, the second dummy nanostructure comprising a superlattice structure, the superlattice structure comprising a second material with a second lattice constant and a third material with a third lattice constant, the first lattice constant being larger than the second lattice constant, and the first lattice constant being smaller than the third lattice constant;
• forming an opening by removing the second dummy nanostructure with an etching process, the etching process removing the second dummy nanostructure at a faster rate than the first dummy nanostructure, the etching process removing the first dummy nanostructure at a faster rate than the semiconductor nanostructure;
• and
• forming an isolation structure in the opening.