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US 12,588,257 B2Granted
2D layered gate oxide
AssigneeIntel Corporation
InventorsChelsey Dorow, Sudarat Lee, Kevin P. O'Brien, Ande Kitamura, Ashish Verma Penumatcha, Carl H. Naylor, Kirby Maxey, Scott B. Clendenning, Uygar E. Avci, Chia-Ching Lin
Life of this patent
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Abstract
Embodiments disclosed herein include transistor devices. In an embodiment, the transistor comprises a transition metal dichalcogenide (TMD) channel. In an embodiment, a two dimensional (2D) dielectric is over the TMD channel. In an embodiment, a gate metal is over the 2D dielectric.
Claims25
A transistor, comprising:
- a transition metal dichalcogenide (TMD) channel;
- a two dimensional (2D) dielectric over the TMD channel;
- and
- a gate metal over the 2D dielectric.
1 more element
A transistor device, comprising:
- a fin;
- a transition metal dichalcogenide (TMD) channel over the fin;
- a two dimensional (2D) dielectric over the TMD channel;
- and
- a gate metal over the 2D dielectric.
2 more elements
An electronic system, comprising:
- a board;
- a package substrate coupled to the board;
- and
- a die coupled to the package substrate, wherein the die comprises:
- a transistor with a transition metal dichalcogenide (TMD) channel that is surrounded by a gate dielectric that comprises a thickness that is approximately 1 nm or less.
2 more elements
Dependencies are inferred from the claim text.