Spacer structures for nano-sheet-based devices

A method comprising:

• forming a first semiconductor layer over a substrate, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer over the second semiconductor layer, wherein:
• the first semiconductor layer and the third semiconductor layer include a first semiconductor material, the second semiconductor layer includes a second semiconductor material, and the second semiconductor material is different than the first semiconductor material,
• the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer extend lengthwise between a first source/drain region and a second source/drain region along a first direction, and
• the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked along a second direction that is different than the first direction;
• forming a gate structure over the third semiconductor layer, wherein the gate structure includes a gate stack having gate spacers, wherein the gate spacers are disposed along sidewalls of the gate stack, the gate structure has a width along the first direction, and each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer has a first length along the first direction after the forming of the gate structure, wherein the first length is substantially the same as the width;
• etching the second semiconductor layer to have a second length along the first direction that is less than the first length, wherein:
• the etching of the second semiconductor layer to have the second length forms a pair of gaps underneath the gate spacers of the gate structure,
• the etching of the second semiconductor layer provides the second semiconductor layer having the second length between a first gap of the pair of gaps and a second gap of the pair of gaps, wherein the first gap has a first gap length along the first direction, the second gap has a second gap length along the first direction, and a sum of the second length, the first gap length, and the second gap length is substantially the same as the width of the gate structure,
• the etching of the second semiconductor layer provides each of the first gap and the second gap between a respective portion of the first semiconductor layer disposed underneath the gate structure and a respective portion of the third semiconductor layer disposed underneath the gate structure, wherein each of the first gap length and the second gap length is equal to a distance between a respective sidewall of the second semiconductor layer having the second length and respective sidewalls of the first semiconductor layer and the third semiconductor layer, and
• the etching of the second semiconductor layer provides each of the first gap and the second gap with a gap width along the second direction;
• depositing a spacer layer that partially fills the first gap and the second gap, wherein the spacer layer covers the sidewalls of the first semiconductor layer, the sidewalls of the third semiconductor layer, and each of the first gap and the second gap is partially filled with a U-shaped portion of the spacer layer, wherein:
• the U-shaped portion includes a first portion that covers a top of the respective portion of the first semiconductor layer disposed underneath the gate structure, a second portion that covers the respective sidewall of the second semiconductor layer having the second length, and a third portion that covers a bottom of the respective portion of the third semiconductor layer disposed underneath the gate structure, and
• the spacer layer has a thickness that is less than the gap width and each of the first portion and the third portion of the U-shaped portion of the spacer layer has a first spacer length along the first direction that is greater than each of the first gap length and the second gap length along the first direction;
• etching back the first portion and the third portion of the U-shaped portion of the spacer layer, wherein the first portion and the third portion of the U-shaped portion of the spacer layer have a second spacer length along the first direction after the etching back, wherein the etching back provides the second spacer length less than each of the first gap length and the second gap length and the etching back provides a sum of the second spacer length and the second length that is less than the first length, wherein:
• the etching back of the first portion and the third portion of the U-shaped portion of the spacer layer includes tuning parameters of an etching process to produce a byproduct that forms polymeric features in a remainder of the first gap and a remainder of the second gap while etching back the first portion and the third portion of the U-shaped portion of the spacer layer, and
• the polymeric features are removed after the etching back;
• forming a first epitaxial source/drain feature and a second epitaxial source/drain feature, wherein the first epitaxial source/drain feature extends into the first gap and underneath the gate structure and the second epitaxial source/drain feature extends into the second gap and underneath the gate structure;
• and
• forming an interlevel dielectric layer over the first epitaxial source/drain feature and the second epitaxial source/drain feature, wherein the interlevel dielectric layer is adjacent to the gate structure.

A method, comprising:

• receiving a semiconductor structure having a first semiconductor layer over a substrate, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer over the second semiconductor layer, wherein the first semiconductor layer and the third semiconductor layer include a first semiconductor material, the second semiconductor layer includes a second semiconductor material, and the second semiconductor material is different than the first semiconductor material;
• performing a first etching process on the second semiconductor layer to form a gap between a top portion of the first semiconductor layer and a bottom portion of the third semiconductor layer;
• depositing a spacer layer over the semiconductor structure, wherein:
• the spacer layer covers the top portion of the first semiconductor layer, a bottom portion of the first semiconductor layer, and a sidewall of the first semiconductor layer that extends between the top portion and the bottom portion of the first semiconductor layer,
• the spacer layer covers the bottom portion of the third semiconductor layer and a sidewall of the third semiconductor layer that extends between the bottom portion and a top portion of the third semiconductor layer,
• a portion of the spacer layer partially fills the gap between the top portion of the first semiconductor layer and the bottom portion of the third semiconductor layer, wherein the portion of the spacer layer has a U-shaped cavity, and
• the depositing of the spacer layer includes tuning the depositing of the spacer layer to provide the spacer layer with a thickness that provides the U-shaped cavity of the portion of the spacer layer with a gap width that is less than a Van der Waals radius of a given etching chemical;
• performing a second etching process on the spacer layer to remove the spacer layer from the sidewall of the first semiconductor layer and the sidewall of the third semiconductor layer and partially remove the portion of the spacer layer having the U-shaped cavity, wherein the second etching process partially removes portions of the spacer layer disposed on the top portion of the first semiconductor layer and the bottom portion of the third semiconductor layer without affecting a portion of the spacer layer disposed on a sidewall of the second semiconductor layer, such that the second etching process laterally recesses the portion of the spacer layer having the U-shaped cavity relative to the sidewall of the first semiconductor layer and the sidewall of the third semiconductor layer and the second etching process provides a lateral distance that is greater than zero between the laterally recessed portion of the spacer layer having the U-shaped cavity and the sidewalls of the first semiconductor layer and the third semiconductor layer, wherein the second etching process uses the given etching chemical having the Van der Waals radius greater than the gap width of the U-shaped cavity of the portion of the spacer layer;
• forming an epitaxial source/drain feature adjacent to the first semiconductor layer and the third semiconductor layer, wherein the epitaxial source/drain feature wraps the first semiconductor layer, the epitaxial source/drain feature wraps the third semiconductor layer, and the epitaxial source/drain feature extends the lateral distance into the gap and contacts the laterally recessed portion of the spacer layer having the U-shaped cavity;
• and
• replacing the second semiconductor layer with a gate stack.