Semiconductor structure including gate stack surrounding or wrapping around plurality of semiconductor layers or nanostructures and method for forming the same

A method for forming a semiconductor structure, comprising:

• alternately stacking a plurality of sacrificial layers and a plurality of channel layers over a first well, wherein a lowermost sacrificial layer is thicker than other sacrificial layers;
• patterning the plurality of sacrificial layers, the plurality of channel layers and the first well to form a first active region;
• forming a first source/drain feature in the first active region, wherein a bottom surface of the first source/drain feature is located between a top surface and a bottom surface of the lowermost sacrificial layer;
• removing the plurality of sacrificial layers;
• and
• forming a first gate stack around the plurality of channel layers.

A semiconductor structure, comprising:

• a first fin element extending in a first direction;
• a first stack of nanostructures vertically stacked over the first fin element;
• a first source/drain feature adjoining a first side of the first stack of nanostructures and over the first fin element;
• a second source/drain feature adjoining a second side of the first stack of nanostructures and extending into the first fin element;
• a dielectric isolation feature vertically sandwiched between the first source/drain feature and the first fin element;
• and
• a first gate stack wrapping around the first stack of nanostructures, wherein a first portion of the first gate stack between the first fin element and a lowermost nanostructure is thicker than a second portion of the first gate stack between adjacent two of the nanostructures.