Asymmetric source and drain contacts for a thin film transistor (TFT) structure

An integrated circuit, comprising:

• a plurality of semiconductor devices;
• an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers;
• and
• a thin film transistor (TFT) structure within one or more interconnect layers of the plurality of stacked interconnect layers, the TFT structure comprising a gate electrode,
• a gate dielectric on the gate electrode,
• a semiconductor region on the gate dielectric,
• one or more dielectric layers over the semiconductor region,
• a dielectric liner having an inner surface facing the semiconductor region and the one or more dielectric layers, and
• first and second conductive contacts that each extend through the one or more dielectric layers and contact a respective portion of the semiconductor region;
• wherein a first contact area between the first conductive contact and a first portion of the semiconductor region is greater than a second contact area between the second conductive contact and a second portion of the semiconductor region by at least 5 nm2, and wherein at least a portion of the second conductive contact is partially on or otherwise touching at least a portion of the inner surface of the dielectric liner.

An integrated circuit, comprising:

• a plurality of semiconductor devices;
• an interconnect region above the plurality of semiconductor devices, the interconnect region comprising a plurality of stacked interconnect layers;
• and
• a thin film transistor (TFT) structure within one or more interconnect layers of the plurality of stacked interconnect layers, the TFT structure comprising
• a gate electrode,
• a gate dielectric on the gate electrode,
• a semiconductor region on the gate dielectric,
• one or more dielectric layers over the semiconductor region, and
• first and second conductive contacts that each extend through the one or more dielectric layers and contact a respective portion of the semiconductor region;
• wherein the first conductive contact extends through a top surface of the semiconductor region at a first depth beneath the top surface of the semiconductor region and the second conductive contact extends through the top surface of the semiconductor region at a second depth beneath the top surface of the semiconductor region, the first depth being at least 1 nm greater than the second depth.