Method for forming via structure with low resistivity

A method for forming a semiconductor device structure, comprising:

• forming a first recessed gate electrode layer and a second recessed gate electrode layer over and surrounded by a first gate dielectric layer and a second gate dielectric layer, respectively;
• removing the first recessed gate electrode layer;
• forming an insulating material over and surrounded by the first gate dielectric layer after removing the first recessed gate electrode layer;
• recessing the insulating material;
• and
• covering each of a top surface of the recessed insulating material and a top surface of the second recessed gate electrode layer with an insulating capping layer.

A method for forming a semiconductor device structure, comprising:

• forming a plurality of gate structures over a substrate, wherein each of the plurality of gate structures comprises:
• a recessed gate electrode layer;
• a conductive capping layer over the recessed gate electrode layer;
• a gate dielectric layer surrounding the recessed gate electrode layer and the conductive capping layer;
• and
• a gate spacer separated from the recessed gate electrode layer by the gate dielectric layer;
• removing the conductive capping layer and the recessed gate electrode layer of a first gate structure of the plurality of gate structures to form an opening;
• forming an insulating material in the opening, wherein a top surface of the insulating material lower than a top surface of the gate dielectric layer and a top surface of the gate spacer of the first gate structure;
• and
• forming a plurality of insulating capping layers over the plurality of gate structures, respectively, wherein a first insulating capping layer of the plurality of insulating capping layers is in the opening and covers the insulating material and a second insulating capping layer of the plurality of insulating capping layers covers the conductive capping layer of a second gate structure of the plurality of gate structures.