US 12,588,232 B2Granted

Semiconductor-element-including memory device

AssigneeUnisantis Electronics Singapore Pte. Ltd.

InventorsNozomu Harada, Koji Sakui

Life of this patent

Estimating the term…

Loading patent…

Abstract

A dynamic flash memory cell includes an Si base material formed of a first channel region and a second channel region. In the Si base material, a first gate insulating layer surrounds the first channel region, and a second gate insulating layer surrounds the second channel region. A first gate conductor layer surrounds the first gate insulating layer, and a second gate conductor layer surrounds the second gate insulating layer. The first gate conductor layer is connected to a plate line PL, and the second gate conductor layer is connected to a word line WL. An N+ layers formed, respectively, on one ends of the Si base materials are connected to a source line, and an N+ layers formed, respectively, on the other ends of the Si base materials are connected to a bit line BL.

Claims11

Dependent claims

A semiconductor memory device comprising:

a first semiconductor base material that extends parallel to and in a horizontal direction relative to a substrate, wherein the first semiconductor base material is formed to have a length measured from a first end of the first semiconductor base material through a second end of the first semiconductor base material and formed to have one type of carriers charged throughout the length of the first semiconductor base material;
a second semiconductor base material that is apart from the first semiconductor base material in a vertical direction and that overlaps the first semiconductor base material in plan view, wherein the second semiconductor base material is formed to have a length measured from a first end of the second semiconductor base material through a second end of the second semiconductor base material and formed to have said one type of carriers charged throughout the length of the second semiconductor base material;
a first impurity layer that has a conductivity type and is connected to the first end of the first semiconductor base material and a second impurity layer that has said conductivity type and is connected to the second end of the first semiconductor base material;
a third impurity layer that has said conductivity type and is connected to the first end of the second semiconductor base material and a fourth impurity layer that has said conductivity type and is connected to the second end of the second semiconductor base material;
a first gate insulating layer that covers a first region of the first semiconductor base material connected to the first impurity layer and a first region of the second semiconductor base material connected to the third impurity layer;
a second gate insulating layer that is connected to the first gate insulating layer and that covers a second region of the first semiconductor base material and a second region of the second semiconductor base material;
a first gate conductor layer that covers the first gate insulating layer and that functions as a common gate of the first semiconductor base material and the second semiconductor base material;
a second gate conductor layer that surrounds the second gate insulating layer surrounding the second region of the first semiconductor base material;
and
a third gate conductor layer that surrounds the second gate insulating layer surrounding the second region of the second semiconductor base material and that is electrically apart from the second gate conductor layer, wherein
voltages applied to the first impurity layer, the second impurity layer, the third impurity layer, the fourth impurity layer, the first gate conductor layer, the second gate conductor layer, and the third gate conductor layer are controlled to perform a memory write operation, a memory read operation, and a memory erase operation.

8 more elements

A semiconductor memory array including a plurality of memory cells arranged in a matrix, each memory cell comprising:

a semiconductor base material formed in a columnar shape to have a longitudinal length, wherein the semiconductor base material includes first and second regions arranged in series in the longitudinal length of the semiconductor base material, wherein the semiconductor base material is formed to have one type of carriers charged throughout the longitudinal length of the semiconductor base material;
a first impurity layer having a conductivity type and connected to one end of the semiconductor base material adjacent to the first region, and a second impurity layer having said conductivity type and connected to the other end of the semiconductor base material adjacent to the second region;
a first gate insulating layer formed to circumferentially surround the first region of the semiconductor base material;
a second gate insulating layer connected in series in the longitudinal direction to the first gate insulating layer, the second gate insulating layer being formed to circumferentially surround the second region of the semiconductor base material;
a first gate conductor layer formed to circumferentially surround the first gate insulating layer;
and
a second gate conductor layer formed to circumferentially surround the second gate insulating layer, the first and second gate conductor layers being arranged in series in the longitudinal direction and separated from each other with no terminal line provided therebetween,
wherein the semiconductor memory array comprises eight (8) memory cells arranged in a matrix of four rows and two columns, the four rows including first, second, third and fourth rows arranged in a column direction in an ordinal sequence, and the two columns including first and second columns arranged in a row direction, wherein:
the eight (8) memory cells include eight (8) first impurity layers all connected to a single source line;
the eight (8) memory cells include eight (8) second impurity layers that include a set of four (4) second impurity layers arranged along the first column and all connected to a single first bit line and another set of four (4) second impurity layers arranged along the second column and all connected to a single second bit line;
the eight (8) memory cells include eight (8) first gate conductor layers all connected to a single plate line;
and
the eight (8) memory cells include eight (8) second gate conductor layers that include four (4) pairs of second gate conductor layers, each pair includes two adjacent second gate conductor layers arranged in a row with an identical ordinal number and connected to each other.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/742,978Filed 12 May 2022
Priority: WO PCT/JP2021/01842714 May 2021
Published: US 2022/0367681 A117 Nov 2022
Granted: 24 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 12/30
Dynamic random access memory [DRAM] devices: dRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
H10D 30/025
Of FETs having insulated gates [IGFET]: of vertical IGFETs
H10B 12/03
For one transistor one-capacitor [1T-1C] memory cells: making the capacitor or connections thereto
H10B 12/05
For one transistor one-capacitor [1T-1C] memory cells: making the transistor