US 12,588,231 B2 · Method of gap filling for semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flowable oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.

Claims19

Dependent claims

A semiconductor device, comprising:

a first semiconductor fin extending a first non-zero height from a semiconductor substrate;
a first source/drain region on the first semiconductor fin;
a first shallow trench isolation (STI) region on the semiconductor substrate, the first STI region being on a first side of the first semiconductor fin;
and
a first dummy fin extending from the first STI region, the first dummy fin having a topmost surface that is level with a topmost surface of the first semiconductor fin, the first dummy fin comprising a first dielectric material having a first material composition and a second dielectric material having a second material composition, the second material composition being different than the first material composition, the second dielectric material extending along a bottom surface, along sidewalls, and along a topmost surface of the first dielectric material.

2 more elements

A semiconductor device, comprising:

a semiconductor substrate;
a shallow trench isolation (STI) region on the semiconductor substrate;
a first semiconductor fin extending from the semiconductor substrate, the first semiconductor fin being on a first side of the STI region and extending a first height having a non-zero value of H above a topmost surface of the STI region;
a first source/drain region extending from the first semiconductor fin;
a second semiconductor fin extending from the semiconductor substrate, the second semiconductor fin being on a second side of the STI region, the second side being opposite the first side;
and
a dummy fin on the STI region, the dummy fin being interposed between the first semiconductor fin and the second semiconductor fin, the dummy fin extending the first height above the topmost surface of the STI region, the topmost surface of the dummy fin being level with the topmost surface of the first semiconductor fin, wherein the dummy fin comprises:
an inner portion, the inner portion being a first dielectric material;
and
an outer portion, the inner portion being interposed between a first sub-portion of the outer portion and a second sub-portion of the outer portion, the outer portion being a second dielectric material, the second dielectric material having a different material composition than the first dielectric material.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/447,618Filed 10 Aug 2023 · division

Priority

20 Aug 2019

Published

US 2023/0387275 A130 Nov 2023

Granted

24 Mar 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification22 codes

H10D 30/0243
Of fin field-effect transistors [FinFET]: using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide…
H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
H10D 62/292
Of igfets: non-planar channels of IGFETs
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…

Family

Application16/545,386Parent of this division · filed 20 Aug 2019

Application17/226,755Parent of this division · filed 9 Apr 2021

US 10,985,266 B2Parent of this division · filed 20 Apr 2021

US 2023/0387275 A1Pre-grant publication · published 30 Nov 2023

US 11,824,104 B2Parent of this division

US 2021/0057540 A1Published application

US 2021/0226038 A1Published application

US 12,588,231 B2This patent

From the US filing history. Foreign family members aren’t listed.

Method of gap filling for semiconductor device

Life of this patent

Method of gap filling for semiconductor device

Life of this patent

Abstract

Claims19