Gate-top dielectric structure for self-aligned contact

A semiconductor structure, comprising:

• a metal gate structure extending length width along a first direction;
• a pair of gate spacer layers sandwiching the metal gate structure along a second direction perpendicular to the first direction;
• a pair of contact etch stop layers sandwiching the pair of gate spacer layers along the second direction;
• and
• a dielectric cap disposed over the metal gate structure, the pair of gate spacer layers, and at least a part of the pair of contact etch stop layers,
• wherein the dielectric cap comprises a top width along the second direction and a bottom width along the second direction,
• wherein the top width is greater than the bottom width,
• wherein a portion of the dielectric cap extends into the metal gate structure.

A method, comprising:

• forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region;
• forming a dummy gate stack over the channel region of the semiconductor element;
• depositing a spacer layer over sidewalls of the dummy gate stack;
• after the depositing of the spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess;
• forming a source/drain feature in the source/drain recess;
• depositing a contact etch stop layer (CESL) over sidewalls of the spacer layer and the source/drain feature;
• depositing an interlayer dielectric (ILD) layer over the CESL;
• performing a first planarization to expose the dummy gate stack;
• replacing the dummy gate stack with a metal gate structure;
• recessing the metal gate structure to form a recess;
• depositing a dielectric layer over the recess;
• performing a second planarization to expose the ILD layer;
• anisotropically etching the source/drain feature, the CESL, the spacer layer, and the dielectric layer to form a contact opening;
• depositing a metal layer over the contact opening to form a source/drain contact;
• and
• performing a third planarization such that the source/drain contact, the CESL and the dielectric layer are coplanar.