1TIR memory with a 3D structure
AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsSylvain Barraud, François Andrieu
Life of this patent
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Abstract
A memory is structured in lines and columns over several superimposed levels. Each level includes an array of memory elements and gate-all-around access transistors, each transistor including a semiconductor nanowire and each gate being insulated from the gates of the other levels. The memory also includes conductive portions, each crossing at least two levels and coupled to first ends of the nanowires of one column of the levels; memory stacks, each crossing the levels and coupled to second ends of the nanowires of the column; first conductive lines, each connected to the conductive portions of the same column; and word lines each extending in the same level while coupling together the gates of the same line and located in said level.
Claims14
A memory including a structure having lines and columns over several superimposed memory levels, each memory level comprising at least one array of memory elements and gate-all-around access transistors, each gate-all-around access transistor including a semiconductor nanowire at least one portion of which is embedded by a gate, each gate being electrically insulated from the gates of the gate-all-around access transistors of the other memory levels, the memory comprising:
- first electrically-conductive portions, each crossing at least two memory levels and being electrically coupled to first ends of the semiconductor nanowires of gate-all-round access transistors belonging to at least one column and one line of each of said at least two memory levels;
- memory stacks, each crossing said at least two memory levels and forming memory elements belonging to at least one column and one line of each of said at least two memory levels, each memory stack comprising at least one memory material layer crossing said at least two memory levels, said at least one memory material layer being disposed between at least one second electrically-conductive portion crossing said at least two memory levels, said at least one second electrically-conductive portion forming a first electrode of said memory elements and at least one electrically-conductive layer forming a second electrode of said memory elements, the electrically-conductive layer crossing said at least two memory levels, and said electrically-conductive layer being disposed against second ends of the semiconductor nanowires of said gate-all-around access transistors belonging to at least one column and one line of each of said at least two memory levels;
- first electrically-conductive lines, each being electrically connected to the first electrically-conductive portions of the same column of the memory;
- second electrically-conductive lines, each being electrically connected to the second electrically-conductive portions of the same column of the memory;
- and
- word lines each extending in the same memory level corresponding to one of said at least two memory levels while electrically coupling together the gates of the access transistors of the same line of the memory and located in said memory level.
A memory including a structure having lines and columns over several superimposed memory levels, each memory level comprising at least one array of memory elements and gate-all-around access transistors, each gate-all-around access transistor including a semiconductor nanowire at least one portion of which is embedded by a gate, each gate being electrically insulated from the gates of the gate-all-around access transistors of the other memory levels, the memory comprising:
- first electrically-conductive portions, each crossing at least two memory levels and each being electrically coupled to a first end of a first nanowire of a first memory level and being coupled to a first end of a second nanowire of a second memory level, the first memory level and the second memory level being superimposed, the first nanowire and the second nanowire being superimposed;
- memory stacks, each crossing said at least two memory levels and forming memory elements, each memory stack comprising at least one memory material layer crossing said at least two memory levels and being disposed between at least one second electrically-conductive portion forming a first electrode of said memory elements and at least one electrically-conductive layer forming a second electrode of said memory elements, said electrically-conductive layer and said least one second electrically-conductive portion each crossing said at least two memory levels, the electrically-conductive layer being arranged against a second end of said first nanowire and being arranged against a second end of said second nanowire;
- first electrically-conductive lines, each being electrically connected to the first electrically-conductive portions of the same column of the memory;
- second electrically-conductive lines, each being electrically connected to the second electrically-conductive portions of the same column of the memory;
- and
- word lines each extending in the same memory level corresponding to one of said at least two memory levels while electrically coupling together the gates of the access transistors of the same line of the memory and located in said memory level.
Dependencies are inferred from the claim text.