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US 12,588,216 B2Granted
Pillar based memory (MRAM) embedded within the buried power rail within a backside power distribution network
AssigneeInternational Business Machines Corporation
InventorsWu-Chang Tsai, Alexander Reznicek, Michael Rizzolo, Ailian Zhao
Life of this patent
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Abstract
An apparatus comprising a backside power distribution network; a backside power rail joined to the backside power distribution network; and a backside contact via that couples at least one front end of line transistor to the backside power rail; wherein the backside contact via comprises a pillar based memory device.
Claims15
An apparatus comprising:
- a transistor comprising a source or drain;
- a backside contact coupled to the source or drain of the transistor, wherein a top surface of the backside contact is directly physically connected to a bottom surface of the source or drain of the transistor;
- and
- a memory device formed at a backside of a wafer, the memory device comprising an electrode;
- wherein the electrode of the memory device is directly physically connected to the backside contact of the transistor.
2 more elements
A method comprising:
- forming, within a first region of a wafer, a first sacrificial placeholder under a source or drain region of at least one transistor of the first region;
- forming, within a second region of the wafer, a second sacrificial placeholder under a source or drain region of at least one transistor of the second region;
- wherein the first sacrificial placeholder is formed deeper within the wafer than the second sacrificial placeholder;
- flipping the wafer;
- removing the first sacrificial placeholder to form a first empty region;
- forming a first backside contact and an electrode for a memory device within at least partially the first empty region, the first backside contact contacting a source or drain of the at least one transistor of the first region;
- depositing and patterning the memory device within at least partially the first empty region;
- removing the second sacrificial placeholder to form a second empty region;
- and
- forming a second backside contact within at least partially the second empty region, the second backside contact contacting a source or drain of the at least one transistor of the second region.
7 more elements
A semiconductor device, comprising:
- a first region comprising a first backside contact to couple at least one transistor of the first region to a memory device of the first region, wherein a top surface of the first backside contact is directly physically connected to a bottom surface source or drain of the at least one transistor;
- and
- a second region comprising a second backside contact to couple at least one transistor of the second region to a backside power rail of the second region.
Dependencies are inferred from the claim text.