# US 12,588,213 B2 · Semiconductor memory structure having enhanced memory window and method for manufacturing the same

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- Number: US 12,588,213 B2
- Document ID: US12588213B2
- Status: Granted
- Kind: B2
- Application number: 18/171,167
- Filed: 2023-02-17
- Published: 2024-03-21
- Granted: 2026-03-24
- Earliest claimed: 2022-09-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Meng-Han Lin; Chia-En Huang; Sai-Hooi Yeong
- Web page: https://patentgrep.com/patent/US12588213B2

## CPC

- H10B 51/30: characterised by the memory core region
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory structure includes a plurality of memory cells arranged in an array. Each of the memory cells includes a memory region, a word line portion disposed on a first surface of the memory region, a first conductive block disposed on a second surface of the memory region opposite to the first surface, a second conductive block disposed on the second surface of the memory region, and a third conductive block disposed on the second surface of the memory region such that the third conductive block is disposed between and separated from the first conductive block and the second conductive block.

## Claims

### Claim 1

A memory structure comprising:
a memory cell including:
a memory region having a first surface and a second surface opposite to each other;
a word line portion disposed on the first surface of the memory region;
a first conductive block disposed on the second surface of the memory region;
a second conductive block disposed on the second surface of the memory region;
a third conductive block disposed on the second surface of the memory region such that the third conductive block is disposed between and separated from the first conductive block and the second conductive block; and
a channel feature disposed to be in contact with the first conductive block and the second conductive block and to separate the first conductive block and the second conductive block from the third conductive block.

### Claim 2 (depends on 1)

The memory structure according to claim 1, wherein the memory cell further includes a dielectric spacer disposed to surround and laterally cover the third conductive block and to separate the third conductive block from the channel feature.

### Claim 3 (depends on 1)

The memory structure according to claim 1, further comprising a dielectric stack region which laterally cover the word line portion and which includes at least one first dielectric portion and at least one second dielectric portion, the first dielectric portion including a first dielectric material, the second dielectric portion including a second dielectric material different from the first dielectric material.

### Claim 4 (depends on 3)

The memory structure according to claim 3, wherein the second dielectric portion has a width less than that of the first dielectric portion.

### Claim 5 (depends on 3)

The memory structure according to claim 3, wherein the first dielectric portion has a lateral surface aligned with a lateral surface of the second dielectric portion.

### Claim 6 (depends on 3)

The memory structure according to claim 3, wherein the second dielectric portion includes a lower surface and a lateral surface which is inclined relative to the lower surface, such that an angle between the lower surface and the lateral surface is an acute angle.

### Claim 7 (depends on 3)

The memory structure according to claim 3, wherein the second dielectric portion includes a lower surface and a lateral surface which is inclined relative to the lower surface, such that an angle between the lower surface and the lateral surface is an obtuse angle.

### Claim 8 (depends on 3)

The memory structure according to claim 3, wherein the second dielectric portion includes a lateral surface configured in a concave shape.

### Claim 9 (depends on 3)

The memory structure according to claim 3, wherein the second dielectric portion includes a lateral surface configured in a convex shape.

### Claim 10 (depends on 3)

The memory structure according to claim 3, wherein the dielectric stack region includes a plurality of the first dielectric portions and a plurality of the second dielectric portions disposed to alternate with the first dielectric portions, a lowermost portion of the dielectric stack region being the first dielectric portion.

### Claim 11 (depends on 3)

The memory structure according to claim 3, wherein the dielectric stack region includes a plurality of the first dielectric portions and a plurality of the second dielectric portions disposed to alternate with the first dielectric portions, a lowermost portion of the dielectric stack region being the second dielectric portion.

### Claim 12 (depends on 1)

The memory structure according to claim 1, wherein the word line portion serves as a gate electrode of the memory cell, the first conductive block serves as a first source/drain electrode of the memory cell, the second conductive block serves as a second source/drain electrode of the memory cell, the third conductive block serves as an assistant gate electrode of the memory cell, and the memory region serves as a gate dielectric of the memory cell.

### Claim 13 (depends on 2)

The memory structure according to claim 2, further comprising a substrate disposed in a manner in which the first conductive block, the second conductive block, the third conductive block, and the channel feature are disposed between the gate electrode and the substrate.

### Claim 14 (depends on 1)

The memory structure according to claim 1, wherein the channel feature serves as a channel of the memory cell.

### Claim 15

A semiconductor device comprising:
a substrate; and
a memory structure disposed over the substrate and including:
a memory film having a first surface and a second surface opposite to the first surface,
a plurality of conductive regions disposed on the first surface of the memory film, the conductive regions being spaced apart from each other in a first direction and extending in a second direction transverse to the first direction,
a plurality of first conductive blocks disposed on the second surface of the memory film, the first conductive blocks being arranged in an array, which include a plurality of columns of the first conductive blocks spaced apart from each other in the first direction, the first conductive blocks in each column being spaced apart from each other in the second direction,
a plurality of second conductive blocks disposed on the second surface of the memory film, the second conductive blocks being arranged in an array, which include a plurality of columns of the second conductive blocks spaced apart from each other in the first direction, the second conductive blocks in each column being spaced apart from each other in the second direction, the plurality of columns of the second conductive blocks being disposed to alternate with and separate from the plurality of columns of the first conductive blocks, and
a plurality of third conductive blocks disposed on the second surface of the memory film, the third conductive blocks being arranged in an array, which includes a plurality of columns of the third conductive blocks spaced apart from each other in the first direction, the third conductive blocks in each column being spaced apart from each other in the second direction, each column of the third conductive blocks being disposed between and spaced apart from a corresponding column of the first conductive blocks and a corresponding column of the second conductive blocks in the first direction, each of the third conductive blocks being disposed between and spaced apart from a corresponding one of the first conductive blocks and a corresponding one of the second conductive blocks in the first direction.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15, further comprising:
a plurality of dielectric spacers disposed on the second surface of the memory film, the dielectric spacers being arranged in an array, which include a plurality of columns of the dielectric spacers spaced apart from each other in the first direction, the dielectric spacers in each column being spaced apart from each other in the second direction, each of the dielectric spacers being disposed to cover a bottom surface and a lateral surface of a corresponding one of the third conductive blocks and to separate the corresponding one of the third conductive blocks from a corresponding one of the first conductive blocks and a corresponding one of the second conductive blocks.

### Claim 17 (depends on 16)

The semiconductor device according to claim 16, further comprising:
a plurality of chancel features disposed on the second surface of the memory film, the channel features being arranged in an array, which include a plurality of columns of the channel features spaced apart from each other in the first direction, the channel features in each column being are spaced apart from each other in the second direction, each of the channel features being disposed to cover a bottom surface and a lateral surface of a corresponding one of the dielectric spacers and to separate the corresponding one of the dielectric spacers from a corresponding one of the first conductive blocks and a corresponding one of the second conductive blocks.

### Claim 18

A method for manufacturing a semiconductor device, comprising:
forming a memory film over a substrate;
forming a plurality of conductive regions on a first surface of the memory film, such that the conductive regions is spaced apart from each other in a first direction and extend in a second direction transverse to the first direction;
forming a plurality of first conductive blocks on a second surface of the memory film, such that the first conductive blocks are arranged in an array, which include a plurality of columns of the first conductive blocks spaced apart from each other in the first direction, the first conductive blocks in each column being spaced apart from each other in the second direction;
forming a plurality of second conductive blocks on the second surface of the memory film, such that the second conductive blocks are arranged in an array, which include a plurality of columns of the second conductive blocks spaced apart from each other in the first direction, the second conductive blocks in each column being spaced apart from each other in the second direction, the plurality of columns of the second conductive blocks being disposed to alternate with and separate from the plurality of columns of the first conductive blocks; and
forming a plurality of third conductive blocks on the second surface of the memory film, such that the third conductive blocks are arranged in an array, which includes a plurality of columns of the third conductive blocks spaced apart from each other in the first direction, the third conductive blocks in each column being spaced apart from each other in the second direction, each column of the third conductive blocks being disposed between and spaced apart from a corresponding column of the first conductive blocks and a corresponding column of the second conductive blocks in the first direction, each of the third conductive blocks being disposed between and spaced apart from a corresponding one of the first conductive blocks and a corresponding one of the second conductive blocks in the first direction.

### Claim 19 (depends on 18)

The method according to claim 18, further comprising forming a plurality of dielectric spacers on the second surface of the memory film, such that the dielectric spacers are arranged in an array, which include a plurality of columns of the dielectric spacers spaced apart from each other in the first direction, the dielectric spacers in each column being spaced apart from each other in the second direction, each of the dielectric spacers being disposed to cover a bottom surface and a lateral surface of a corresponding one of the third conductive blocks and to separate the corresponding one of the third conductive blocks from a corresponding one of the first conductive blocks and a corresponding one of the second conductive blocks.

### Claim 20 (depends on 19)

The method according to claim 19, further comprising forming a plurality of channel features on the second surface of the memory film, such that the channel features are arranged in an array, which include a plurality of columns of the channel features spaced part from each other in the first direction, the chancel features in each column being spaced apart from each other in the second direction, each of the channel features being disposed to cover a bottom surface and a lateral surface of a corresponding one of the dielectric spacers and to separate the corresponding one of the dielectric spacers from a corresponding one of the first conductive blocks and a corresponding one of the second conductive blocks.