Three-dimensional memory device containing insulated gate located over a top source layer for applying GIDL erase voltage and method for manufacturing the same
AssigneeSanDisk Technologies LLC
InventorsTakaaki Iwai, Shinsuke Yada, Satoshi Shimizu
Life of this patent
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Abstract
A memory device includes a source layer, an alternating stack of insulating layers and electrically conductive layers located over a proximal horizontal surface of the source layer, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, a source-control-gate dielectric located over a distal horizontal surface of the source layer which is opposite to the proximal surface of the source layer, and a source-control electrode located over the source-control-gate dielectric.
Claims20
A memory device, comprising:
- a source layer;
- an alternating stack of insulating layers and electrically conductive layers located over a proximal horizontal surface of the source layer;
- a memory opening vertically extending through the alternating stack;
- a memory opening fill structure located in the memory opening and comprising a memory film and a vertical semiconductor channel;
- a source-control-gate dielectric located over a distal horizontal surface of the source layer which is opposite to the proximal surface of the source layer;
- and
- a source-control electrode located over the source-control-gate dielectric.
A method of forming a memory device, comprising:
- forming an alternating stack of insulating layers and spacer material layers over a proximal horizontal surface of a source layer, wherein the spacer material layers are formed as or are subsequently replaced with electrically conductive layers;
- forming a memory opening through the alternating stack;
- forming a memory opening fill structure in the memory opening, wherein the memory opening fill structure comprises a memory film and a vertical semiconductor channel;
- forming a tubular cavity by removing a portion of the memory film that is proximal to a distal horizontal surface of the source layer that is opposite to the proximal horizontal surface of the source layer;
- forming a tubular source strap in the tubular cavity;
- exposing a distal portion of an inner sidewall of the vertical semiconductor channel;
- forming a source-control-gate dielectric on the distal portion of the inner sidewall of the vertical semiconductor channel and on the distal horizontal surface of the source layer;
- and
- forming a source-control electrode over the source-control-gate dielectric.
Dependencies are inferred from the claim text.