US 12,588,207 B2 · Semiconductor device including channel structures and a slit structure

Abstract

A semiconductor device includes a gate structure including a cell region and a contact region, a slit structure configured to extend in a first direction through the gate structure, first channel structures disposed in the cell region of the gate structure, and second channel structures disposed in the cell region of the gate structure and disposed to be more adjacent to the contact region of the gate structure than the first channel structures. In a second direction that intersects the first direction, the first channel structures may be spaced apart from the slit structure by a first distance, and the second channel structures may be spaced apart from the slit structure at a second distance.

Claims16

Dependent claims

A semiconductor device comprising:

a gate structure comprising a cell region and a contact region;
a slit structure configured to extend in a first direction through the gate structure;
first channel structures disposed in the cell region of the gate structure;
and
second channel structures disposed in the cell region of the gate structure and disposed to be more adjacent to the contact region of the gate structure than the first channel structures,
wherein in a second direction that intersects the first direction, the first channel structures are spaced apart from the slit structure by a first distance, and the second channel structures are spaced apart from the slit structure at a second distance, the second distance is greater than the first distance.

3 more elements

A semiconductor device comprising:

a first gate structure comprising a cell region and a contact region;
first channel structures and second channel structures disposed in the cell region of the first gate structure;
a second gate structure disposed on the first gate structure;
third channel structures disposed within the second gate structure and connected to the first channel structures;
fourth channel structures disposed within the second gate structure and connected to the second channel structures;
and
a slit structure disposed within the first gate structure and the second gate structure and configured to extend in a first direction,
wherein in a second direction that intersects the first direction, the first channel structures are spaced apart from the slit structure by a first distance, and the second channel structures are spaced apart from the slit structure by a second distance that is greater than the first distance.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/339,857Filed 22 Jun 2023

Priority

KR 10-2023-002430723 Feb 2023

Published

US 2024/0292615 A129 Aug 2024

Granted

24 Mar 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout

Semiconductor device including channel structures and a slit structure

Life of this patent

Semiconductor device including channel structures and a slit structure

Life of this patent

Abstract

Claims16