Non-volatile memory device and electronic system including the same

A non-volatile memory device comprising:

• a substrate comprising a cell array region and an extension region;
• a mold structure comprising a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate, wherein the mold structure has a step shape that steps downwardly in the extension region in a direction away from the cell array region;
• first and second interlayer insulating layers sequentially stacked on the mold structure;
• a channel structure penetrating through the mold structure in the cell array region;
• a cell contact structure penetrating through the mold structure and the first interlayer insulating layer in the extension region, wherein the cell contact structure is in contact with a side surface of an uppermost one of the gate electrodes, a top surface of the uppermost one of the gate electrodes, and a side surface of the first interlayer insulating layer;
• and
• an insulating ring between the cell contact structure and another one of the gate electrodes, wherein the insulating ring extends around the cell contact structure,
• wherein the cell contact structure comprises a first surface in contact with the side surface of the uppermost one of the gate electrodes and a second surface in contact with the side surface of the first interlayer insulating layer,
• wherein a width of the cell contact structure having the first surface in contact with the side surface of the uppermost one of the gate electrodes is smaller than a width of the cell contact structure having the second surface in contact with the side surface of the first interlayer insulating layer, and
• wherein an etch rate of the first interlayer insulating layer is greater than an etch rate of the second interlayer insulating layer.

An electronic system comprising:

• a main board;
• a non-volatile memory device on the main board;
• and
• a controller electrically connected to the non-volatile memory device,
• wherein the non-volatile memory device comprises:
• a substrate comprising a cell array region and an extension region;
• a mold structure comprising a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the substrate, wherein the mold structure has a step shape that steps downwardly in the extension region in a direction away from the cell array region;
• first and second interlayer insulating layers sequentially stacked on the mold structure;
• a channel structure penetrating through the mold structure in the cell array region;
• and
• a cell contact structure penetrating through the mold structure and the first interlayer insulating layer in the extension region,
• wherein the cell contact structure comprises a first portion in contact with a side surface of an uppermost one of the gate electrodes and a second portion in contact with a top surface of the uppermost one of the gate electrodes and a side surface of the first interlayer insulating layer,
• wherein a width of the first portion is smaller than a width of the second portion, and
• wherein an etch rate of the first interlayer insulating layer is greater than an etch rate of the second interlayer insulating layer.