Semiconductor memory devices with one-sided staircase profiles and methods of manufacturing thereof

A method of making a semiconductor die, comprising:

• providing a stack comprising a plurality of insulating layers and a plurality of sacrificial layers alternatively stacked on top of each other in a vertical direction;
• forming a first interface portion on a first end and a second interface portion on a second end of the stack opposite to the first end in a first horizontal direction;
• forming an array of device structures between the first and second interface portions, wherein the first and second interface portions include first and second staircase profiles, respectively;
• forming a plurality of first trenches into at least a bottommost layer of the stack, the plurality of first trenches extending in the first horizontal direction and a second trench extending in a second horizontal direction perpendicular to the first horizontal direction and having sidewalls substantially coplanar or vertical with the array of device structures, with each of the plurality of first trenches being intersected by the second trench;
• and
• filling the plurality of first trenches and the second trench with an insulating material,
• wherein forming the second trench divides the array of device structures into a first sub-array of device structures adjacent to the first staircase profile and a second sub-array of device structures adjacent to the second staircase profile, and (i) a first pair of the first sub-array of device structures and the first staircase profile and (ii) a second pair of the second sub-array of device structures and the second staircase profile are spaced from each other in the first horizontal direction by only the second trench filled with the insulating material.

A method of making a semiconductor die, comprising:

• providing a stack comprising a plurality of insulating layers and a plurality of sacrificial layers alternatively stacked on top of each other in a vertical direction;
• forming a first interface portion on a first end and a second interface portion on a second end of the stack opposite to the first end in a first horizontal direction, wherein the first interface portion and the second interface portion have first and second staircase profiles, respectively, in the vertical direction;
• forming an array of device structures between the first and second interface portions;
• concurrently forming a plurality of first trenches into at least a bottommost layer of the stack, the plurality of first trenches extending in the first horizontal direction and a second trench extending in a second horizontal direction perpendicular to the first horizontal direction and having sidewalls substantially coplanar or vertical with the array of device structures, wherein each of the plurality of first trenches is intersected by the second trench;
• and
• filling the plurality of first trenches and the second trench with an insulating material,
• wherein the second trench divides the array of device structures into a first sub-array of device structures adjacent to the first staircase profile and a second sub-array of device structures adjacent to the second staircase profile in the first horizontal direction, and wherein (i) a first pair of the first sub-array of device structures and the first staircase profile and (ii) a second pair of the second sub-array of device structures and the second staircase profile are spaced from each other in the first horizontal direction by only the second trench filled with the insulating material.