US 12,588,190 B2 · Semiconductor device with a low-k spacer and method for fabricating the same

Abstract

Embodiments of present invention provide a semiconductor device capable of reducing parasitic capacitance between neighboring pattern structures and a method for fabricating the same. Also, embodiments of the present invention provide a semiconductor device capable of preventing device deterioration due to carbon diffusion and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device comprises a bit line structure including a bit line contact plug and a bit line stacked over a substrate; a lower spacer structure including a diffusion barrier layer and a first low-k layer sequentially stacked over both sidewalls of the bit line contact plug; and an upper spacer structure including a second low-k layer over both sidewalk of the bit line.

Claims17

Dependent claims

A semiconductor device comprising:

a bit line structure including a bit line contact plug and a bit line stacked over a substrate;
a lower spacer structure including a diffusion barrier layer and a first low-k layer sequentially stacked over both sidewalls of the bit line contact plug;
and
an upper spacer structure including a second low-k layer contacted with both sidewalls of the bit line,
wherein the diffusion barrier layer is directly contacted with the both sidewalls of the bit line contact plug and includes a carbon-free silicon nitride,
wherein the second low-k layer includes silicon-based material containing a carbon impurity.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor device with a low-k spacer and method for fabricating the same

Life of this patent

Semiconductor device with a low-k spacer and method for fabricating the same

Life of this patent

Abstract

Claims17