Memory devices with vertical transistors

An integrated circuit (IC) device, comprising:

• a substrate, the substrate having a first surface and a second surface, the second surface opposite the first surface;
• a first region as one of a source region and a drain region of a transistor, the first region comprising a first semiconductor material with first dopants and extending from the first surface towards the second surface, wherein a width of the first region at a first distance from the first surface is larger than the width of the first region at a second distance from the first surface, and the second distance is shorter than the first distance;
• a second region as another one of the source region and the drain region, the second region comprising a second semiconductor material with second dopants;
• a channel region between the first region and the second region;
• and
• a control line of a memory device, the control line comprising an electrically conductive material, wherein a portion of the control line wraps around a portion of the channel region,
• wherein a concentration of the first dopants in the first region is at least 106 times higher than a concentration of dopants in the channel region.