Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a substrate having a substrate groove extending in a first direction;
• a gate insulating layer conformally covering an inner wall of the substrate groove;
• a metal-containing pattern on the gate insulating layer and filling a lower portion of the substrate groove;
• a silicon pattern on the metal-containing pattern in the substrate groove;
• and
• a word line capping pattern on the silicon pattern in the substrate groove,
• wherein the silicon pattern includes:
• a first silicon pattern covering an upper surface of the metal-containing pattern and a side surface of the gate insulating layer and having a pattern groove formed thereon;
• and
• a second silicon pattern filling the pattern groove, and
• wherein the first silicon pattern has a first silicon grain average size, and the second silicon pattern has a second silicon grain average size greater than the first silicon grain average size.

A semiconductor device comprising:

• a substrate having a substrate groove extending in a first direction;
• a gate insulating layer conformally covering an inner wall of the substrate groove;
• a metal-containing pattern on the gate insulating layer and filling a lower portion of the substrate groove;
• a silicon pattern on the metal-containing pattern in the substrate groove;
• a word line capping pattern on the silicon pattern in the substrate groove;
• a first impurity region in the substrate at one side of the word line capping pattern;
• a second impurity region in the substrate on the other side of the word line capping pattern;
• a bit line extending in a second direction crossing the first direction on the substrate and connected to the first impurity region;
• a bit line contact between the bit line and the first impurity region;
• a bit line capping pattern on the bit line;
• a storage node contact on the second impurity region;
• and
• a landing pad on the storage node contact and partially covering the bit line capping pattern,
• wherein the silicon pattern includes:
• a first silicon pattern covering an upper surface of the metal-containing pattern and a sidewall of the gate insulating layer and having a pattern groove formed thereon;
• a second silicon pattern filling the pattern groove;
• and
• a void region positioned between the first silicon pattern and the second silicon pattern,
• wherein:
• the first silicon pattern has a first thickness at the sidewall of the gate insulating layer,
• the second silicon pattern has a first width, and
• the first thickness is 0.8 to 1.2 times the first width.