Semiconductor memory device and method for fabricating the same

A semiconductor memory device comprising:

• a substrate including a cell region and a peripheral region surrounding the cell region, the cell region including a cell active region;
• a cell element separation film on the substrate and defining the cell active region;
• a cell gate structure disposed at the substrate of the cell region, wherein the cell gate structure includes:
• a cell gate trench extending in a first direction across the cell element separation film and the cell active region, wherein the cell gate trench extends from an upper surface of the cell element separation film toward a bottom surface of the substrate, and
• a cell gate electrode in the cell gate trench;
• a bit line structure disposed at the substrate of the cell region, wherein the bit line structure includes:
• a cell conductive line extending in a second direction different from the first direction, and
• a cell line capping film disposed on the cell conductive line;
• a plurality of fin-type patterns disposed at the substrate of the peripheral region, extending in the first direction, and being spaced apart from each other in the second direction;
• a fin trench separating the plurality of fin-type patterns adjacent to each other in the second direction from each other, wherein the fin trench extends from an upper surface of a first fin-type pattern of the plurality of fin-type patterns adjacent to the fin trench toward the bottom surface of the substrate;
• a peripheral gate electrode crossing the plurality of fin-type patterns;
• and
• a peripheral interlayer insulating film disposed on the peripheral gate electrode,
• wherein a depth of the cell gate trench relative to the upper surface of the cell element separation film is the same as a depth of the fin trench relative to the upper surface of the first fin-type pattern of the plurality of fin-type patterns adjacent to the fin trench.

A semiconductor memory device comprising:

• a substrate including a cell region and a peripheral region surrounding the cell region, the cell region including a cell active region;
• a plurality of cell gate electrodes disposed at the substrate of the cell region and extending in a first direction;
• a bit line structure disposed at the substrate of the cell region, wherein the bit line structure includes:
• a cell conductive line extending in a second direction different from the first direction, and
• a cell line capping film disposed on the cell conductive line;
• a plurality of fin-type patterns disposed at the substrate of the peripheral region, extending in the first direction, and being spaced apart from each other in the second direction;
• a plurality of fin trenches separating the plurality of fin-type patterns from each other and being spaced apart from each other in the second direction;
• a peripheral gate electrode crossing the plurality of fin-type patterns;
• and
• a peripheral interlayer insulating film disposed on the peripheral gate electrode,
• wherein an interval between two adjacent cell gate electrodes of the plurality of cell gate electrodes spaced apart from each other in the second direction is the same as an interval between two adjacent fin trenches of the plurality of fin trenches spaced apart from each other in the second direction.