Memory device using semiconductor element

A memory device using a semiconductor element, the memory device comprising:

• a first semiconductor region;
• a first impurity region that exists on the first semiconductor region;
• a second semiconductor region that contacts the first impurity region and that extends in a vertical direction;
• a first gate insulating layer that covers a portion of the second semiconductor region;
• a first gate conductive layer that contacts the first gate insulating layer;
• a first insulating layer that is formed so as to contact the first gate conductive layer and the first gate insulating layer;
• a third semiconductor region that contacts the second semiconductor region and whose vertical cross section is recessed;
• a second gate insulating layer that is formed along at least a recessed portion of the third semiconductor region and whose vertical cross section is recessed;
• a second gate conductive layer that is formed on an inner side of a recessed portion of the second gate insulating layer;
• and
• a second impurity region and a third impurity region that are each formed so as to contact an upper surface of a corresponding one of protruding portions of the recessed portion of the third semiconductor region,
• wherein a contact surface where the third semiconductor region and the second impurity region contact each other or a contact surface where the third semiconductor region and the third impurity region contact each other exits at a position lower than a surface of the second gate conductive layer.