Method of fabricating semiconductor memory device including capping layer

A method of fabricating a semiconductor memory device, the method comprising:

• providing a substrate that includes a cell array region and a boundary region;
• forming a device isolation layer that defines a plurality of active sections on an upper portion of the substrate on the cell array region;
• forming an intermediate layer on the substrate on the boundary region;
• forming on the substrate on the cell array region and the boundary region an electrode layer that covers the intermediate layer on the boundary region;
• forming a capping layer on the electrode layer;
• forming an additional capping pattern including providing a first step difference to the capping layer on the boundary region;
• and
• allowing the additional capping pattern, the capping layer, and the electrode layer to proceed an etching process to form a plurality of bit lines that run across the active sections,
• wherein a thickness of the capping layer on the cell array region is greater than a thickness of the capping layer on the boundary region,
• wherein, during the etching process, a top surface of the electrode layer is simultaneously exposed on the cell array region and the boundary region, and
• wherein, during the etching process, the thickness of the capping layer on the cell array region is the same as a height from a bottom surface of the capping layer on the boundary region to a top surface of the additional capping pattern on the boundary region.