Four-poly-pitch SRAM cell with backside metal tracks

A semiconductor structure, comprising:

• a memory cell comprising:
• a first active region and a second active region extending lengthwise along a first direction, and
• a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure each extending lengthwise along a second direction different from the first direction;
• a first isolation feature adjacent to the first active region and extending lengthwise along the first direction;
• and
• a second isolation feature adjacent to the second active region and extending lengthwise along the first direction,
• wherein each of the second gate structure and the third gate structure straddles the first and second active regions and extends between the first isolation feature and the second isolation feature, and wherein, in a top view, a dimension of the second gate structure along the second direction is equal to a distance between the first isolation feature and the second isolation feature.

A semiconductor structure, comprising:

• a first transistor comprising:
• a first plurality of nanostructures over a substrate,
• a gate structure wrapping around and over the first plurality of nanostructures, and
• a first source/drain feature and a second source/drain feature coupled to the first plurality of nanostructures;
• a first backside via disposed under and coupled to the first source/drain feature;
• a bit line disposed under and electrically coupled to the first backside via;
• a word line over and electrically coupled to the gate structure;
• and
• a second transistor comprising the second source/drain feature and a third source/drain feature;
• a second backside via disposed under and electrically coupled to the third source/drain feature;
• and
• a power line disposed under and electrically coupled to the second backside via.