Fly bitline design for pseudo triple port memory

A memory, comprising:

• a semiconductor substrate;
• a bitcell on the semiconductor substrate, the bitcell having a bitcell width and a bitcell height and including a first access transistor and a second access transistor;
• a zero metal (M0) layer patterned to form a pair of local bitlines within the bitcell width, the pair of local bitlines including a local bitline coupled to a first terminal of a local data path (LDP) and including a complement local bitline coupled to a second terminal of the LDP;
• a first metal layer adjacent the semiconductor substrate, the first metal layer patterned to form a first pair of wordlines arranged within the bitcell height, the first pair of wordlines including a first wordline coupled to a gate of the first access transistor and including a second wordline coupled to a gate of the second access transistor;
• a second metal layer adjacent the M0 layer and the first metal layer, the second metal layer patterned to form a pair of second metal layer islands within the bitcell width, the pair of second metal layer islands including a first island coupled to the first wordline and a second island coupled to the second wordline;
• and
• a third metal layer adjacent the second metal layer, the third metal layer patterned to form a pair of third metal layer interconnects, including a first interconnect coupled to the first island and a second interconnect coupled to the second island.