Multi-chip accelerator architecture for fully homomorphic encryption inference

A non-transitory computer-readable medium storing instructions that, when executed by one or more processors of a system, cause the processors to perform operations comprising:

• distributing session-initialization data over an interconnect for a large-language-model session;
• operating a first plurality of application-specific integrated circuits to perform bootstrapping on ciphertexts during an initiation phase;
• and
• operating a second plurality of application-specific integrated circuits by:
• (i) causing bootstrapping circuitry to store auxiliary data used during bootstrapping and to perform bootstrapping operations on ciphertexts;
• (ii) causing processing circuitry to perform homomorphic arithmetic operations other than bootstrapping;
• and (iii) causing support circuitry to perform functions that support the bootstrapping and processing circuitry;
• and
• wherein the system comprises:
• a plurality of server modules, the interconnect operatively coupled to each of the server modules, the first plurality of application-specific integrated circuits disposed on one or more of the server modules, and the second plurality of application-specific integrated circuits disposed on the server modules-;
• and
• wherein the instructions, when executed, further cause the bootstrapping circuitry to perform modulus adjustment, coefficient-to-slot conversion, slot-to-coefficient conversion, and re-linearization on the ciphertexts without, or with reduced, access to volatile memory located external to the bootstrapping circuitry.