US 12,587,356 B2Granted

Accelerator device and operating method of accelerator device

AssigneeElectronics and Telecommunications Research Institute

InventorSeong-Cheon Park

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Abstract

Disclosed is an accelerator device, which includes a first NTT converter that performs an NTT operation on a first ciphertext of a first type to generate a first internal signal, a test polynomial generator that generates a test polynomial, a second NTT converter that performs the NTT operation on the test polynomial to generate a second internal signal, a first multiplier that performs a multiplication on the first internal signal and the second internal signal to generate a third internal signal, a first INTT converter that performs an INTT operation on the third internal signal to generate a fourth internal signal, a gadget decomposer that performs a gadget decomposition on the fourth internal signal to generate a fifth internal signal, and a third NTT converter that performs the NTT operation on the fifth internal signal to generate a sixth internal signal.

Claims19

Dependent claims

A computing device comprising:

memory;
a processor configure to execute code stored in the memory to:
perform a Number Theoretic Transform (NTT) operation on a first ciphertext of a first type received from an external device to generate a first internal signal;
generate a test polynomial;
perform the NTT operation on the test polynomial to generate a second internal signal;
perform multiplication on the first internal signal and the second internal signal to generate a third internal signal;
perform an inverse NTT (INTT) operation on the third internal signal to generate a fourth internal signal;
perform a gadget decomposition on the fourth internal signal to generate a fifth internal signal;
perform the NTT operation on the fifth internal signal to generate a sixth internal signal;
perform the NTT operation on a first ciphertext of a second type received from the external device to generate a seventh internal signal;
perform multiplication on the sixth internal signal and the seventh internal signal to generate an eighth internal signal;
perform the INTT operation on the eighth internal signal to generate a ninth internal signal;
and
accumulate the ninth internal signal to generate a second ciphertext of the first type.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/351,163Filed 12 Jul 2023
Priority: KR 10-2022-008541412 Jul 2022
Published: US 2024/0022393 A118 Jan 2024
Granted: 24 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H04L 9/008
Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols: involving homomorphic…
H04L 9/3093
Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy: involving…
H04L 2209/125
Details relating to cryptographic hardware or logic circuitry: parallelization or pipelining, e.g. for accelerating processing of cryptographic…
H04L
Digital communication