System and method of digital to analog conversion with improved linearity and accuracy

A method of digital to analog conversion, comprising:

• modulating a digital value DN−K with an oversampling delta sigma modulator to provide an M-bit coarse quantized value DM, wherein DN−K comprises N−K least significant bits of an N-bit digital input value DN;
• adding the DM value to a digital value DK to provide a digital select value DKM, wherein the DK value comprises the K remaining most significant bits of the DN value;
• and
• applying mismatch shaping of a total of at least P=2K elements of a P-element digital to analog converter (DAC) per cycle based on the DKM value and providing an analog output value;
• wherein the applying mismatch shaping comprises:
• using a data-weighted averaging algorithm for selecting DKM elements from among a total of the P elements of the P-element DAC per cycle;
• and
• summing outputs of selected elements for providing the analog output value;
• wherein the using a data-weighted averaging algorithm comprises outputting a set of P complementary binary signals each having a first state when selected or a second state when not selected;
• wherein the selecting comprises controlling each of a parallel set of P current-steering circuits by a corresponding one of the set of P complementary binary signals for providing a corresponding one of a set of P bidirectional current signal pairs;
• and
• wherein the summing outputs comprises summing outputs of the set of P bidirectional current signal pairs for providing the analog output value as a differential signal.

A method of digital to analog conversion, comprising:

• modulating a digital value DN−K with an oversampling delta sigma modulator to provide an M-bit coarse quantized value DM, wherein DN−K comprises N−K least significant bits of an N-bit digital input value DN;
• adding the DM value to a digital value DK to provide a digital select value DKM, wherein the DK value comprises the K remaining most significant bits of the DN value;
• and
• applying mismatch shaping of a total of at least P=2K elements of a P-element digital to analog converter (DAC) per cycle based on the DKM value and providing an analog output value;
• wherein the applying mismatch shaping comprises:
• selecting DKM elements from among a total of the P elements of the P-element DAC per cycle;
• and
• summing outputs of selected elements for providing the analog output value;
• wherein the applying mismatch shaping comprises outputting a set of P complementary binary signals each having a first state when selected or a second state when not selected;
• wherein the selecting comprises controlling each of a parallel set of P current-steering circuits by a corresponding one of the set of P complementary binary signals for providing a corresponding one of a set of P bidirectional current signal pairs;
• and
• wherein the summing outputs comprises summing outputs of the set of P bidirectional current signal pairs for providing the analog output value as a differential signal.