Channel selection circuit, analog-to-digital converter and system-on-chip
AssigneeGigadevice Semiconductor Inc.
InventorLipeng Wu
Life of this patent
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Abstract
A channel selection circuit, an analog-to-digital converter (ADC) and a system-on-chip (SoC) are provided. During a sampling phase of an ADC circuit, a substrate voltage of a MOS switch in a selected channel is set to a voltage of analog input signal to which the channel is coupled. This eliminates the body-bias effect of the MOS switch, greatly improving linearity of the channel selection circuit and enabling the ADC to provide the required high speed and high-accuracy and exhibit excellent performance even at a low power supply voltage. Moreover, harmonic distortion around the dominant frequency can be suppressed, enabling the ADC to provide the required high accuracy (e.g., a 16-bit or even higher resolution).
Claims20
A channel selection circuit serving as a front-end circuit of an analog-to-digital conversion (ADC) circuit, wherein the channel selection circuit comprises:
- a switch control circuit, configured to generate first switch control signals based on channel selection signals during a sampling phase of the ADC circuit;
- a MOS switch channel circuit comprising an input terminal coupled to m analog input signals and an output terminal coupled to an input terminal of the ADC circuit, wherein the MOS switch channel circuit has m channels each having a MOS switch, wherein a gate of each MOS switch is coupled to a corresponding one of the first switch control signals;
- and
- a substrate potential control circuit comprising:
- input terminals coupled to the m analog input signals and the first switch control signals;
- and output terminals coupled to substrates of the MOS switches in the MOS switch channel circuit, wherein the substrate potential control circuit is configured to set, during the sampling phase of the ADC circuit, a substrate voltage of the MOS switch in a selected channel to a voltage of the analog input signal to which the selected channel is coupled.
An analog-to-digital converter (ADC) comprising an analog-to-digital conversion (ADC) circuit and a channel selection circuit,
- wherein the channel selection circuit comprises:
- a switch control circuit, configured to generate first switch control signals based on channel selection signals during a sampling phase of the ADC circuit;
- a MOS switch channel circuit comprising an input terminal coupled to m analog input signals and an output terminal coupled to an input terminal of the ADC circuit, wherein the MOS switch channel circuit has m channels each having a MOS switch, wherein a gate of each MOS switch is coupled to a corresponding one of the first switch control signals;
- and
- a substrate potential control circuit comprising:
- input terminals coupled to the m analog input signals and the first switch control signals;
- and output terminals coupled to substrates of the MOS switches in the MOS switch channel circuit, wherein the substrate potential control circuit is configured to set, during the sampling phase of the ADC circuit, a substrate voltage of the MOS switch in a selected channel to a voltage of the analog input signal to which the selected channel is coupled,
- wherein the channel selection circuit is coupled to the m analog input signals and is configured to select one of the m analog input signals each time and output the selected analog input signal to an input terminal of the ADC circuit, and wherein the ADC circuit is configured to convert the analog input signal selected by the channel selection circuit into a digital signal.
A system-on-chip (SoC) comprising an analog-to-digital converter (ADC), wherein the ADC comprises an analog-to-digital conversion (ADC) circuit and a channel selection circuit,
- wherein the channel selection circuit comprises:
- a switch control circuit, configured to generate first switch control signals based on channel selection signals during a sampling phase of the ADC circuit;
- a MOS switch channel circuit comprising an input terminal coupled to m analog input signals and an output terminal coupled to an input terminal of the ADC circuit, wherein the MOS switch channel circuit has m channels each having a MOS switch, wherein a gate of each MOS switch is coupled to a corresponding one of the first switch control signals;
- and
- a substrate potential control circuit comprising:
- input terminals coupled to the m analog input signals and the first switch control signals;
- and output terminals coupled to substrates of the MOS switches in the MOS switch channel circuit, wherein the substrate potential control circuit is configured to set, during the sampling phase of the ADC circuit, a substrate voltage of the MOS switch in a selected channel to a voltage of the analog input signal to which the selected channel is coupled,
- wherein the channel selection circuit is coupled to the m analog input signals and is configured to select one of the m analog input signals each time and output the selected analog input signal to an input terminal of the ADC circuit, and wherein the ADC circuit is configured to convert the analog input signal selected by the channel selection circuit into a digital signal.
Dependencies are inferred from the claim text.