Duty cycle correction circuit and duty cycle correcting method
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsByoungwoon Lee, Jian Luo, Hang Song
Life of this patent
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Abstract
A duty cycle correction circuit can comprise at least one low pass filter configured to convert a clock signal to a voltage, and a voltage comparator configured to compare the voltage with a reference voltage to output a comparison signal. The duty cycle correction circuit can further comprise a controller configured to select, based on the comparing voltage, a duty cycle correction method from a first method and a second method different from the first method. The duty cycle correction circuit can further comprise a duty regulator configured to perform a duty tuning operation to adjust a duty of the clock signal using the selected duty cycle correction method.
Claims20
A method for duty cycle correction, comprising:
- performing a first loop of duty tuning operations to a clock signal by using a first approximation method;
- in response to determining that a first loop count of the first loop reaches a first threshold value, or determining that a duty cross occurs, performing a second loop of duty tuning operations to the clock signal by using a second approximation method different from the first approximation method;
- in response to determining that a second loop count of the second loop reaches a second threshold value, executing a duty check to the clock signal;
- and
- in response to determining that the clock signal has a duty within a target range, passing the duty cycle correction.
A circuit for duty cycle correction, comprising:
- at least one filter configured to convert a clock signal to a voltage;
- a voltage comparator configured to compare the voltage with a reference voltage to output a comparison signal;
- a controller configured to select, based on the comparing voltage, a duty cycle correction method from a first approximation method and a second approximation method different from the first approximation method;
- and
- a duty regulator configured to perform a duty tuning operation to adjust a duty of the clock signal using the selected duty cycle correction method.
A memory system, comprising:
- a memory device;
- and
- a peripheral circuit configured to control the memory device, the peripheral circuit comprising a duty cycle correction circuit, wherein the duty cycle correction circuit comprises:
- at least one low pass filter configured to convert a clock signal to a voltage,
- a voltage comparator configured to compare the voltage with a reference voltage to output a comparison signal,
- a controller configured to select, based on the comparing voltage, a duty cycle correction method from a first approximation method and a second approximation method different from the first approximation method, and
- a duty regulator configured to perform a duty tuning operation to adjust a duty of the clock signal using the selected duty cycle correction method.
Dependencies are inferred from the claim text.