Clock signal circuits

A clock signal circuit for generating first and second non- overlapping output clock signals, the clock signal circuit comprising:

• first and second PMOSFETS;
• first and second NMOSFETs;
• a clock signal input node connected to a gate of the first PMOSFET and a gate of the second NMOSFET;
• a first voltage rail connected to a source of the first PMOSFET;
• a second voltage rail connected to a source of the second NMOSFET;
• a first clock signal output node connected to a drain of the first PMOSFET, a drain of the first NMOSFET and a source of the second PMOSFET;
• and
• a second clock signal output node connected to a drain of the second PMOSFET, a source of the first NMOSFET and a drain of the second NMOSFET;
• third and fourth PMOSFETS;
• third and fourth NMOSFETS;
• an inverted clock signal input node connected to a gate of the third PMOSFET and a gate of the fourth NMOSFET;
• a third clock signal output node connected to a drain of the third PMOSFET, a drain of the third NMOSFET and a source of the fourth PMOSFET;
• and
• a fourth clock signal output node connected to a drain of the fourth PMOSFET, a source of the third NMOSFET and a drain of the fourth NMOSFET.