Linear gate current buffer for parallel power device driving applications

A method of operating a power transistor, the method comprising:

• operating a current buffer as a current amplifier that results in a voltage at a first control terminal of the power transistor, the current buffer having a second control terminal;
• detecting that a drain current through the power transistor is below a threshold current level while the power transistor is turned on;
• in response to detecting that the drain current through the power transistor is below the threshold current level while the power transistor is turned on, opening a first switch and closing a second switch to generate a turn off voltage at the first control terminal and opening a third switch, a first circuit branch including the first switch for opening and closing the first circuit branch, a second circuit branch including the second switch and a first current source that generates a first current having a first current level, wherein the second switch is configured to open and close the second circuit branch, a third circuit branch including the third switch for opening and closing the third circuit branch and a second current source, wherein the second current source generates a second current having a second current level and the second current level is less than the first current level;
• opening the second switch and the third switch and closing the first switch to prevent a Miller capacitance of the power transistor from activating the power transistor;
• detecting that the drain current through the power transistor is above the threshold current level while the power transistor is turned on;
• and
• in response to detecting that the drain current through the power transistor is above the threshold current level while the power transistor is turned on, closing the third switch and opening the first switch and the second switch to prevent the Miller capacitance of the power transistor from activating the power transistor.

A motor system that includes a field effect transistor (FET) driving block, the FET driving block comprising:

• a power transistor having a first control terminal, a first transistor terminal, and a second transistor terminal;
• a current buffer being configured as a current amplifier that results in a voltage at the first control terminal, the current buffer having a second control terminal;
• and
• a driver circuit having a first circuit branch connected to the second control terminal and a second circuit branch connected to the second control terminal, wherein:
• the first circuit branch includes a first switch for opening and closing the first circuit branch;
• and
• the second circuit branch includes a second switch and a first current source, wherein the second switch is configured to open and close the second circuit branch, and the first current source generates a first current having a first current level;
• a third circuit branch including a third switch for opening and closing the third circuit branch and a second current source, wherein the second current source generates a second current having a second current level, and the second current level is less than the first current level.