Reduced power consumption compute-in-memory system, method of operating same

A method of reducing power consumption in a compute-in-memory (CIM) system, the method comprising:

• during an i_th cycle of a first clock signal, doing as follows including:
• detecting that a first scenario is true in which all bits b(k) of a multibit data signal equal logical zero, where i and k are corresponding integers;
• and
• when the first scenario is true, suppressing performance of latching by a first leader-follower (L/F) flip-flop (FF), at least one bit b(k) of the data signal having been equal to logical one during an i−1_th cycle of a first clock signal,
• the first L/F FF being configured to receive the data signal and generate a multibit output signal, the first L/F FF including a first leader FF configured to receive the data signal and generate a signal first_Q_lead, and a first follower FF configured to receive the signal first_Q_lead and generate a signal first_Q_follow that represents the output signal of the first L/F FF;
• and
• when the first scenario is true, for a multiplication unit configured to receive a multibit weight signal and the signal first_Q_follow and generate a first product signal,
• controlling the multiplication unit to generate the first product signal as all bits being equal to logical zero.

A compute-in-memory (CIM) system comprising:

• a first leader-follower (L/F) flip-flop (FF) configured to receive a multibit data signal and generate a multibit output signal, the first L/F FF including:
• a first leader FF configured to receive the data signal and generate a signal first_Q_lead, and
• a first follower FF configured to receive the signal first_Q_lead and generate a signal first_Q_follow that represents the output signal of the first L/F FF;
• at an i−1_th cycle of a first clock signal, at least one bit b(k) of data signal being equal to logical one, where i and k are corresponding integers;
• a multiplier configured to receive a multibit weight signal and the signal first_Q_follow and generate a first product signal;
• and
• a suspender unit configured, during an i_th cycle of the first clock signal, to do as follows including:
• detect that a first scenario is true in which all bits b(k) of the data signal equal logical zero;
• and
• when the first scenario is true,
• trigger a reset operation to be performed by the first L/F FF such that all bits of the signal first_Q_follow are made equal to logical zero.