Fault detection system and method for switched capacitor converter

A method comprising:

• during a startup sequence of a switched capacitor converter:
• detecting, by fault detection circuitry coupled to the switched capacitor converter, a fault in the switched capacitor converter based on second terminal voltages of a plurality of flying capacitors of the switched capacitor converter, the plurality of flying capacitors having first terminals and second terminals, wherein detecting the fault comprises:
• determining, by the fault detection circuitry, that at least one of the second terminal voltages of the plurality of flying capacitors indicates a capacitor plate short based on comparisons of each of the second terminal voltages to a threshold voltage while the second terminals are coupled to a reference potential and while the first terminals are coupled to an output voltage of a battery;
• and
• disabling, by the fault detection circuitry, the switched capacitor converter in response to detecting the fault.

A system comprising:

• fault detection circuitry configured to receive voltages from a plurality of capacitors of a switched capacitor converter, the plurality of capacitors having first terminals and second terminals, and the fault detection circuitry comprising logic circuitry being configured to:
• monitor the voltages in a first state of a startup sequence and a second state of the startup sequence;
• assert a first fault signal in response to determining that any of the voltages is greater than a first threshold voltage while in the first state;
• and
• assert a second fault signal in response to determining that any of the voltages is less than a second threshold voltage while in the second state, wherein the plurality of capacitors comprises a plurality of flying capacitors of the switched capacitor converter, and wherein voltages received by the fault detection circuitry comprise second terminal voltages of the second terminals of the plurality of flying capacitors, and wherein the fault detection circuitry further comprises a finite state machine (FSM) configured to:
• receive the first fault signal and the second fault signal from the logic circuitry;
• and
• disable the switched capacitor converter in response to assertion of either of the first fault signal or the second fault signal.