Memory device and operation method thereof, memory system, and computer system

An operation method of a memory device, comprising:

• in response to a first memory cell row comprised in the memory device indicated by an input address signal being determined to be faulty, generating a first redundant selection signal;
• in response to the first redundant selection signal, causing a corresponding redundant control switch component in the memory device to be in an on state and transmitting a corresponding redundant control signal to a corresponding word line drive component in the memory device;
• and
• in response to the redundant control signal, causing the word line drive component to drive a second memory cell row in the memory device that is configured to replace the first memory cell row.

A memory system, comprising:

• at least one memory device, each of the at least one memory device comprising:
• a memory array comprising a first sub-array and a second sub-array, wherein the first sub-array comprises a plurality of first memory cell rows, and the second sub-array comprises a plurality of second memory cell rows;
• and
• a peripheral circuit coupled to the plurality of first memory cell rows and the plurality of second memory cell rows and comprising:
• a plurality of redundant control switch components coupled to the plurality of second memory cell rows one-to-one;
• and
• a word line drive component coupled to each of the plurality of redundant control switch components, wherein
• each of the redundant control switch components is configured to:
• in response to a first redundant selection signal, be in an on state and transmit a corresponding redundant control signal to a corresponding word line drive component, wherein the first redundant selection signal is generated when a first memory cell row indicated by input address information is determined to be faulty;
• and
• the corresponding word line drive component is configured to:
• in response to the redundant control signal, drive a second memory cell row of the plurality of second memory cell rows that is configured to replace the first memory cell row indicated by the input address information;
• and
• a memory controller coupled to the memory device and configured to control the memory device.

A computer system, comprising:

• a memory system, comprising:
• at least one memory device, each of the at least one memory device comprising:
• a memory array comprising a first sub-array and a second sub-array, wherein the first sub-array comprises a plurality of first memory cell rows, and the second sub-array comprises a plurality of second memory cell rows;
• and
• a peripheral circuit coupled to the plurality of first memory cell rows and the plurality of second memory cell rows and comprising:
• a plurality of redundant control switch components coupled to the plurality of second memory cell rows one-to-one;
• and
• a word line drive component coupled to each of the plurality of redundant control switch components, wherein
• each of the redundant control switch components is configured to:
• in response to a first redundant selection signal, be in an on state and transmit a corresponding redundant control signal to a corresponding word line drive component, wherein the first redundant selection signal is generated when a first memory cell row indicated by input address information is determined to be faulty;
• and
• the corresponding word line drive component is configured to:
• in response to the redundant control signal, drive a second memory cell row of the plurality of second memory cell rows that is configured to replace the first memory cell row indicated by the input address information;
• and
• a memory controller coupled to the memory device and configured to control the memory device;
• and
• a graphics processing unit coupled to the memory system and configured to control the memory system.