Column redundancy data circuits and methods for higher transmit speed
AssigneeSanDisk Technologies LLC
InventorsA. Harihara Sravan, Akash Kamat, Anushree Singla
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Abstract
An apparatus is provided that includes a memory structure including non-volatile memory cells that include a plurality of columns, each column including a column address, and a column redundancy system coupled to the memory structure and a clock signal. The column redundancy system is configured to in a first cycle of the clock signal first compare a first input column address to a first pair of defective column addresses received during an immediately preceding cycle of the clock signal, second compare the first input column address to a second pair of defective column addresses received during the first cycle of the clock signal.
Claims20
An apparatus comprising:
- a memory structure comprising non-volatile memory cells that include a plurality of columns, each column comprising a column address;
- and
- a column redundancy system coupled to the memory structure and a clock signal, the column redundancy system configured to:
- in a first cycle of the clock signal:
- first compare a first input column address to a first pair of defective column addresses received during an immediately preceding cycle of the clock signal;
- and
- second compare the first input column address to a second pair of defective column addresses received during the first cycle of the clock signal.
An apparatus comprising:
- a memory structure comprising non-volatile memory cells comprising a plurality of columns, each column comprising a column address;
- a control circuit coupled to the memory structure, the control circuit configured to:
- receive a first pair of pointers to a first pair of defective column addresses;
- receive a second pair of pointers to a second pair of defective column addresses;
- compare an input column address with the first pair of defective column addresses to generate a first match result;
- compare the input column address with the second pair of defective column addresses to generate a second match result;
- and
- based on one of the first match result or the second match result, increment one of the first pair of pointers or the second pair of pointers, respectively.
A method comprising:
- providing a memory structure comprising non-volatile memory cells that include a plurality of columns, each column comprising a column address, and a plurality of data latches comprising defective column addresses;
- and
- during each cycle of a clock signal:
- comparing an input column address with a first pair of defective column addresses from the plurality of data latches and a second pair of defective column addresses from the plurality of data latches;
- and
- upon determining that the input column address matches one of the first pair of defective column addresses or the second pair of defective column addresses, incrementing pointers to a next first pair of defective column addresses or a next second pair of defective column addresses, respectively;
- wherein at least one of the first pair of defective column addresses and the second pair of defective column addresses was retrieved from the plurality of data latches during a previous cycle of the clock signal.
Dependencies are inferred from the claim text.