Self-calibration in a memory device
AssigneeMicron Technology, Inc.
InventorsJennifer E. Taylor, Eric J. Stave, Timothy M. Hollis, Chulkyu Lee, Chris Gregory Holub
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Abstract
Systems and methods include self-training an equalizer of a semiconductor device using the semiconductor device. The semiconductor device receives an indication of a condition for re-training of the equalizer. The semiconductor device operates the equalizer based on trained values derived during the self-training. The semiconductor device also determines that the condition has been met, and in response, the semiconductor device re-trains the equalizer without invocation of re-training by a host device coupled to the semiconductor device.
Claims19
A method, comprising:
- self-training an equalizer of a semiconductor device using the semiconductor device;
- at the semiconductor device, receiving an indication of a condition for re-training of the equalizer;
- operating the equalizer based on trained values derived during the self-training;
- determining, using the semiconductor device, that the condition has been met;
- and
- re-training the equalizer by the semiconductor device without invocation of re-training by a host device coupled to the semiconductor device, wherein re-training comprises determining tap coefficients to be used in the equalizer.
A semiconductor device, comprising:
- a receiver configured to receive data bits from another device and to latch at least some of the data bits in parallel in a first set of latches using a first reference voltage and in a second set of latches using a second reference voltage;
- and
- self-calibration circuitry, comprising:
- analysis circuitry configured to compare respective parallel-latched bits to determine whether to increment a bit counter;
- averaging circuitry comprising the bit counter configured to track the number of increments determined in the analysis circuitry, and the averaging circuitry is configured to track the number of bit comparisons performed in the analysis circuitry;
- adder/subtractor circuitry configured to add a value to or subtract the value from a present setting based on the number of increments counted to generate a new setting;
- and
- a reference voltage generator to convert the new setting to generate the first reference voltage.
Self-calibration circuitry configured to perform self-training in a memory device, wherein the self-calibration circuitry comprises:
- an input configured to receive first and second latched bits captured from a single bit received at the memory device;
- analysis circuitry to compare the first and second latched bits to determine to increment a first bit counter based on a comparison of the first and second latched bits;
- digital averaging circuitry comprising:
- the first bit counter configured to track the number of increments determined in the analysis circuitry;
- and
- a second bit counter configured to track the number of bit comparisons performed in the analysis circuitry;
- adder/subtractor circuitry configured to:
- receive a step size signal that indicates an incremental value;
- receive an indication of a previous setting of an equalizer;
- and
- add the incremental value to or subtract the incremental value from the previous setting to output a new setting based at least in part on the step size signal, the indication of the previous setting, and the number of increments counted in the first bit counter;
- and
- a reference voltage generator to convert the new setting to generate a reference voltage.
Dependencies are inferred from the claim text.