Memory failure analysis based on bitline threshold voltage distributions

A system, comprising:

• a memory;
• and
• a processor, coupled to the memory, the processor configured to:
• receive a first component line dataset associated with a first memory device;
• receive a first post-fabrication testing dataset comprising a first bitline threshold voltage distribution associated with the first memory device;
• create a training dataset comprising the first component line dataset and the first post-fabrication testing dataset;
• and
• train, using the training dataset, a component line model to predict, based on a second component line dataset associated with a second memory device and a second post-fabrication testing dataset comprising a second bitline threshold voltage distribution associated with the second memory device, a second failure type distribution to be exhibited in a field by the second memory device.

A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a controller of a system comprising one or more memory devices, cause the controller to:

• receive a first component line dataset associated with a first memory device;
• receive a first failure-related dataset comprising a first bitline threshold voltage distribution associated with the first memory device;
• create a training dataset comprising the first component line dataset and the first failure-related dataset;
• and
• train, using the training dataset, a workload prediction model to predict, based on a second component line dataset associated with a second memory device and a second bitline threshold voltage distribution associated with the second memory device, a second post-fabrication testing dataset to be applied to the second memory device in order to yield a post-fabrication testing outcome that would match, with a predefined accuracy, a filed-observable outcome for the second memory device.