System and method for periodic march test in volatile memories
AssigneeBlack Sesame Technologies Inc.
InventorsQideng Yu, Gengyuan Zhang, Wei Chen, Ying Zhou
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Abstract
The disclosure provides a method for performing self-test on a memory. The method can include determining an operation mode of a memory built-in self-test (MBIST) unit based on status of the memory; in response to the operation mode being a startup mode, configuring the MBIST unit to perform a memory self-test of a first type; and in response to the operation mode being a runtime mode, configuring the MBIST unit to periodically perform a memory self-test of a second type.
Claims18
A method for performing self-tests on a memory, the method comprising:
- determining an operation mode of a memory built-in self-test (MBIST) unit based on a status of the memory;
- in response to the operation mode being a startup mode, configuring the MBIST unit to perform a memory self-test of a first type;
- and
- in response to the operation mode being a runtime mode, configuring the MBIST unit to periodically perform a memory self-test of a second type, wherein periodically performing the memory test of the second type comprises:
- detecting that a processor associated with the memory enters a periodic interval, during which the processor is not accessing the memory;
- and
- performing the memory self-test of the second type during the periodic interval.
A memory built-in self-test (MBIST) system for performing a self-test on a memory, comprising:
- a controller for interfacing with a processor associated with the memory;
- and
- a MBIST engine coupled to the controller;
- wherein the controller is to configure an operation mode of the MBIST engine based on a status of the memory;
- and
- wherein the MBIST engine is configured to:
- generate a test pattern of a first type in response to the operation mode being a startup mode;
- periodically generate a test pattern of a second type in response to the operation mode being a runtime mode;
- perform memory read and write operations based on the generated test pattern of the first or second type;
- and
- trigger the memory self-test using the test pattern of the second type in response to the controller detecting that the processor enters a periodic interval, during which the processor is not accessing the memory.
Dependencies are inferred from the claim text.