Quick pass write with quasi-low verify high level

A controller in communication with a memory apparatus including memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage corresponding to one of a plurality of data states and disposed in memory holes each coupled to one of a plurality of bit lines, the controller configured to:

• instruct the memory apparatus to apply each of a plurality of program pulses to selected ones of the plurality of word lines;
• and
• following each of the plurality of program pulses and for each one of the memory cells, instruct the memory apparatus to determine whether the threshold voltage of the one of the memory cells detected exceeds a lower verify level and a higher verify level of one of the plurality of data states targeted while applying one of a plurality of verify bit line voltages to ones of the plurality of bit lines coupled to the memory cells being programmed, the one of the plurality of verify bit line voltages selected based on the threshold voltage of the one of the memory cells relative to one of the lower verify level and the higher verify level.

A method of operating a memory apparatus including memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage corresponding to one of a plurality of data states and disposed in memory holes each coupled to one of a plurality of bit lines, the method comprising the steps of:

• applying each of a plurality of program pulses to selected ones of the plurality of word lines;
• and
• following each of the plurality of program pulses and for each one of the memory cells, determining whether the threshold voltage of the one of the memory cells detected exceeds a lower verify level and a higher verify level of one of the plurality of data states targeted while applying one of a plurality of verify bit line voltages to ones of the plurality of bit lines coupled to the memory cells being programmed, the one of the plurality of verify bit line voltages selected based on the threshold voltage of the one of the memory cells relative to one of the lower verify level and the higher verify level.