Storage device with word lines applied with respective voltage levels during different time periods

A storage device comprising:

• a first wiring;
• a first select transistor connected to the first wiring;
• a second select transistor;
• a first memory cell transistor and a second memory cell transistor connected in series between the first select transistor and the second select transistor;
• a first word line connected to the first memory cell transistor;
• and
• a second word line connected to the second memory cell transistor,
• wherein the storage device is configured such that, during a first period in which a first voltage is applied to the first wiring, a second voltage lower than the first voltage is applied in parallel to the first word line and the second word line,
• wherein the storage device is configured such that, during a second period in which a third voltage higher than the first voltage is applied to the first wiring, the second voltage is applied to the first word line, and a fourth voltage higher than the second voltage and lower than the third voltage is applied to the second word line,
• wherein the storage device is configured such that, during a third period in which the third voltage is applied to the first wiring, the fourth voltage is applied to the first word line, and the second voltage is applied to the second word line, and
• wherein the second period and the third period are shorter than the first period.