Memory device
AssigneeKioxia Corporation
InventorHideto Takekida
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a memory device includes: a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a second conductive layer that are arranged in this order in a first direction, spaced apart from each other; a first semiconductor film extending in the first direction, being in contact with the first semiconductor layer and the second semiconductor layer, and intersecting the first conductive layer and the second conductive layer; a first memory film provided between the first conductive layer and the first semiconductor film; and a second memory film provided between the second conductive layer and the first semiconductor film.
Claims19
A memory device comprising:
- a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a second conductive layer that are arranged in this order in a first direction, spaced apart from each other;
- a first semiconductor film extending in the first direction, being in contact with the first semiconductor layer and the second semiconductor layer, and intersecting the first conductive layer and the second conductive layer;
- a first memory film provided between the first conductive layer and the first semiconductor film;
- and
- a second memory film provided between the second conductive layer and the first semiconductor film.
A memory device comprising:
- a first memory cell transistor and a second memory cell transistor coupled in series;
- a first source line electrically coupled to a first end of the first memory cell transistor;
- a first bit line electrically coupled to a second end of the first memory cell transistor and a first end of the second memory cell transistor;
- a second bit line electrically coupled to a second end of the second memory cell transistor;
- a first word line electrically coupled to a gate of the first memory cell transistor;
- and
- a second word line electrically coupled to a gate of the second memory cell transistor.
Dependencies are inferred from the claim text.