Precharge scheme during programming of a memory device

A memory device, comprising:

• at least one memory block, the at least one memory block having a source side and a drain side and including a plurality of memory cells arranged in a plurality of word lines, and the plurality of word lines being arranged in a plurality of sub-blocks that are configured to be programmed and erased independently of one another;
• and
• control circuitry configured to program the memory cells of a selected sub-block of the plurality of sub-blocks, the control circuitry being configured to;
• determine a location of a selected sub-block of the plurality of sub-blocks within the at least one memory block and a programming condition of at least one unselected sub-block of the plurality of sub-blocks,
• program at least one word line in the selected sub-block in a plurality of program loops, the program loops including pre-charging processes, and wherein the control circuitry pre-charges a plurality of channels in the at least one memory block from either the source side or the drain side of the at least one memory block based on at least one of the location of the selected sub-block within the at least one memory block and the programming condition of the at least one unselected sub-block, and
• sequentially program the word lines of the selected sub-block of the plurality of sub-blocks in a direction from the drain side towards the source side of the at least one memory block regardless of the location of the selected sub-block within the at least one memory block and regardless of the programming condition of the at least one unselected sub-block.

An apparatus, comprising:

• at least one memory block, the at least one memory block having a source side and a drain side and including a plurality of memory cells arranged in a plurality of word lines, and the plurality of word lines being arranged in a plurality of sub-blocks that are configured to be programmed and erased independently of one another;
• and
• a programming means for programming the memory cells of the at least one memory block to include at least three bits of data per memory cell, when programming a selected sub-block of the plurality of sub-blocks, the programming means being configured to;
• determine a location of a selected sub-block of the plurality of sub-blocks within the at least one memory block and determine a programming condition of at least one unselected sub-block of the plurality of sub-blocks,
• program a selected word line in the selected sub-block in a plurality of program loops, the program loops including programming pulses and verify operations,
• during each of the verify operations, apply a pass voltage VREAD to a plurality of unselected word lines,
• begin discharging the unselected word lines on one side of a selected word line one after the other to remove electrons from a plurality of channels of the at least one memory block on one side of the selected word line, and
• sequentially program the word lines of the selected sub-block of the plurality of sub-blocks in a direction from the drain side towards the source side of the at least one memory block regardless of the location of the selected sub-block within the memory block and regardless of the programming condition of the at least one unselected sub-block.