Sense amplifier circuit, corresponding memory device and method of operation

A sense amplifier circuit for a memory device, comprising:

• a first input terminal and a second input terminal configured for coupling to a first memory sensing node and a second memory sensing node, respectively;
• a comparator circuit comprising:
• a first input node and a second input node;
• a first output node and a second output node configured to produce a first output current and a second output current, respectively;
• a first input transistor having a conductive channel arranged between said first input node and said first output node of the comparator circuit, and a first control terminal coupled to an internal biasing node;
• a second input transistor having a conductive channel arranged between said second input node and said second output node of the comparator circuit, and a second control terminal coupled to said internal biasing node;
• wherein said first input node and said second input node of the comparator circuit are selectively couplable to each other in response to assertion of a compensation signal, and selectively couplable to said first and second input terminals, respectively, in response to de-assertion of said compensation signal;
• wherein said internal biasing node is selectively couplable to a comparator biasing node in response to assertion of a bias enable signal, and selectively left floating in response to de-assertion of said bias enable signal;
• a sensing circuit coupled to said first output node and to said second output node of the comparator circuit, said sensing circuit configured to produce a memory reading signal as a function of a difference between said first output current and said second output current.