Resistive memory and operating method thereof

A memory, comprising:

• a first select transistor configured to provide a voltage signal to a first node, and comprising a first doped region;
• a first resistor configured to store a first data bit according to the voltage signal, a first terminal of the first resistor being coupled to the first node;
• a second resistor configured to store a second data bit different from the first data bit according to the voltage signal, a first terminal of the second resistor being coupled to the first node;
• a first transistor configured to output a first bit line signal corresponding to the first data bit and the second data bit, and comprising a first gate structure, a control terminal of the first transistor being coupled to the first node;
• a first electrode extending along a first direction, and configured to couple the first gate structure and the first doped region;
• a first dielectric layer extending along the first direction;
• a second dielectric layer extending along the first direction and sandwiched between the first dielectric layer and the first electrode;
• a second electrode contacting the first dielectric layer;
• and
• a third electrode contacting the first dielectric layer, and separated from the second electrode along the first direction.

An operating method of a memory, comprising:

• providing a first voltage signal having a first voltage level to a first node by a first select transistor;
• storing a first data bit by a first resistor, wherein a first terminal of the first resistor is coupled to the first node;
• storing a second data bit different from the first data bit by a second resistor, wherein a first terminal of the second resistor is coupled to the first node;
• storing a third data bit by a third resistor, wherein a first terminal of the third resistor is coupled to a second node;
• connecting each of a second terminal of the first resistor and a second terminal of the third resistor to a first word line signal;
• and
• outputting a bit line signal corresponding to the first data bit, the second data bit and the third data bit by a first transistor and a second transistor, wherein a control terminal of the first transistor is coupled to the first node, and a control terminal of the second transistor is coupled to the second node,
• wherein the first resistor corresponds to a first portion of a first dielectric layer and a second portion of a second dielectric layer,
• the second resistor corresponds to a third portion of the first dielectric layer and a fourth portion of the second dielectric layer,
• the second portion contacts the first portion and a first electrode, and
• the fourth portion contacts the third portion and a second electrode, and the second electrode is separated from the first electrode.