In-memory computation device for performing a signed MAC operation

A method for controlling an in-memory computation (IMC) device to perform a multiply-and-accumulate (MAC) operation, said IMC device including a computation memory array comprising a plurality of groups of memory cells coupled to a bitline, the method comprising:

• storing a respective computational weight having a sign and an absolute value in each group of memory cells, wherein each group of memory cells includes a positive memory cell coupled to a respective positive wordline and a negative memory cell coupled to a respective negative wordline;
• activating the positive memory cell by a respective positive-activation signal on the respective positive wordline;
• activating the negative memory cell by a respective negative-activation signal on the respective negative wordline;
• flowing a respective positive-cell current by the respective positive memory cell for each group of memory cells in response to the respective positive-activation signal;
• flowing a respective negative-cell current by the respective negative memory cell for each group of memory cells in response to the respective negative-activation signal;
• wherein, for each group of memory cells, a combination of the respective positive-cell current and the respective negative-cell current is equal to a total current and wherein a difference between the respective positive-cell current and the respective negative-cell current is a function of the sign and the absolute value of the respective computational weight stored by the group of memory cells;
• providing during an elaboration interval having an elaboration duration, in response to an input signal indicative of a plurality of input values each having a respective sign and a respective absolute value, for each input value, the positive-activation signal having a positive-activation duration to the positive wordline of a respective group of memory cells and the negative-activation signal having a negative-activation duration to the negative wordline of the respective group of memory cells;
• wherein, for each input value, the elaboration duration comprises a combination of the respective positive-activation duration and the respective negative-activation duration;
• wherein the difference between the respective positive-activation duration and the respective negative-activation duration is a function of the sign and of the absolute value of the respective input value;
• flowing a bitline current through the bitline coupled to the groups of memory cells during the elaboration interval that is a function of the sum of the positive-cell currents and the negative-cell currents of the groups of memory cells coupled to the bitline;
• and
• sampling the bitline current and providing, in response thereto, at least one output signal.